Principal SerDes Design Engineer

Celero Communications, Inc.; Ottawa; On-site; CAD 140,000 - 220,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architectural definition and implementation of next-generation SerDes for high-speed transceivers.

The role emphasizes system-level modelling, behavioral analysis, and close collaboration across teams. The candidate will drive design of analog/mixed-signal blocks, with emphasis on CTLE, DFE,PLL reliability, and integration into SOCs, while overseeing lab validation and performance optimization in a

Qualifications

• Master’s or PhD in Electrical Engineering with 10+ years in SerDes design.
• Proven track record of tape-out and volume production of high-speed SerDes.
• Experience with lab bring-up, characterization and debugging for production.
• Experience with advanced node technologies (16nm/12nm to 2nm).
• Cross-functional IP delivery and seamless SOC integration.

Responsibilities

• Define architecture, specifications and topologies for next-generation SerDes.
• Model system-level behavior, analyze link budgets, equalization and jitter budgeting.
• Design high-performance analog/mixed-signal circuits in advanced nodes.
• Develop critical blocks: RX/TX, CTLE, DFE, PLLs, interpolators, DLLs, TDCs.
• Oversee layout to minimize parasitics and process variation impacts.
• Lead lab validation, debugging and characterization of SerDes IPs.
• Correlate silicon with simulations and optimize system performance.

Skills

High-speed SerDes design

System-level thinking

Cross-functional collaboration

Communication skills

Analog/mixed-signal design

Education

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

SystemVerilog

Verilog-A

Job description

Principal SerDes Design Engineer

About the job

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills

Javier Leon
Talent Acquisition
619-227-3193 cell/text
[e-mail]
www.celero.inc