ASIC Digital Design, Principal Engineer-18731

Synopsys, Inc.; Mississauga; On-site; CAD 120,000 - 180,000; Full time

Job summary

Synopsys, Inc. in Mississauga, Ontario, is seeking a senior ASIC verification leader to drive strategy, execution, and quality for next-generation PCIe PHY IP verification.

You are an experienced verification engineer with a track record in high-speed SerDes-based PHYs, PCIe architectures, and coverage-driven verification. You will mentor peers and collaborate with design, analog, firmware, and systems teams to deliver robust IP solutions.

Qualifications

• Experience in mixed-signal ASIC/IP verification.
• Strong PCIe/PCIe PHY verification background.
• Deep knowledge of SerDes/PHY architectures and digital verification.
• Proficient with SystemVerilog, UVM, assertions, and coverage.
• Ability to design verification plans and reusable environments.
• Excellent debugging and problem-solving skills.
• Strong cross-functional collaboration and mentoring.

Responsibilities

• Define verification strategy and quality for PCIe PHY IPs.
• Develop verification plans for complex mixed-signal designs.
• Architect and execute advanced testbench environments.
• Verify PCIe PHY features: LTSSM, PIPE, link init/training, power, equalization.
• Collaborate with design, analog, firmware, architecture, and validation teams.
• Apply constrained-random, assertion-based, coverage-driven verification and debug automation.
• Analyze failures and drive root-cause resolutions.
• Mentor engineers and promote verification best practices.
• Communicate goals and deliverables to stakeholders.

Skills

PCIe verification

Mixed-signal verification

SystemVerilog

UVM

Assertions

Coverage-driven verification

Testbench development

Debugging

Communication skills

Mentoring

Job description

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to intelligent systems. We are a leader in chip design, verification, and IP integration, enabling customers to accelerate innovation and bring high-performance silicon and software solutions to market faster.

Our team develops high-speed silicon IP solutions with a primary focus on PCIe PHY technology. These IPs enable customers to integrate advanced connectivity into SoCs faster while meeting demanding performance, power, area, and reliability targets. We are looking for a senior verification leader to drive the strategy, execution, and quality of next-generation PCIe PHY IP verification.

You Are

You are an experienced ASIC Verification Engineer with a strong track record of delivering high-quality mixed-signal IP products, especially high-speed SerDes-based PHYs. You bring deep expertise in digital verification methodologies and have strong domain knowledge in PCIe PHY architectures, link behavior, LTSSM, power management, equalization, and interoperability requirements.

You are comfortable defining and driving verification strategy for complex PHY IPs, building scalable verification environments, and collaborating closely with design, analog, systems, and architecture teams. You are a proactive problem solver who can work with minimal supervision, communicate clearly across technical disciplines, and lead verification efforts that improve product quality and execution efficiency.

What You’ll Be Doing

• Define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.


• Develop comprehensive verification plans for complex mixed-signal digital designs with primary emphasis on PCIe PHY functionality and protocol compliance.


• Architect, develop, and execute advanced testbench environments for block-level and subsystem-level verification.


• Verify key PCIe PHY features such as LTSSM behavior, PIPE interface interactions, link initialization and training, power management, equalization flows, error handling, and compliance-related scenarios.


• Work closely with design, analog, firmware, architecture, and validation teams to ensure robust coverage of cross-functional use cases.


• Use advanced verification methodologies, including constrained-random, assertion-based verification, coverage-driven verification, and debug automation, to achieve high-quality results.


• Analyze failures, root-cause complex issues, and drive resolution across design and verification domains.


• Mentor and guide other engineers, promote verification best practices, and help build a culture of technical excellence and continuous improvement.


• Communicate effectively with internal stakeholders and customers to align on technical goals, verification quality, and deliverables.

What You’ll Need

• Extensive experience in mixed-signal ASIC/IP verification.


• Strong expertise in PCIe and PCIe PHY verification.


• Solid understanding of high-speed SerDes/PHY architecture and digital control verification in mixed-signal environments.


• Hands-on experience with modern verification methodologies such as SystemVerilog, UVM, assertions, and coverage-driven verification.


• Experience developing verification plans, building reusable verification environments, and closing coverage for complex IP products.


• Strong debugging and problem-solving skills, with the ability to work independently and drive issues to closure.


• Excellent communication and collaboration skills for working across global, cross-functional teams.


• Proven ability to mentor engineers and lead technical verification activities.

Who You Are

• A technical leader who can drive verification excellence for complex PCIe PHY IP products.


• A mentor who develops talent, shares knowledge, and raises the bar for the team.


• A proactive problem solver who thrives in technically challenging environments.


• A strong communicator who can clearly convey complex concepts to both technical and cross-functional audiences.


• A collaborative team player who values innovation, quality, and execution. #L1-NK4