Principal SerDes Design Engineer

Celero Communications, Inc.; Vancouver; On-site; CAD 150,000 - 210,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer in Vancouver to architect and lead high-speed SerDes development for next-generation transceivers.

The role focuses on system-level modelling, verification, and integration of analog/mixed-signal blocks in cutting-edge node technologies. You will oversee layout, lab validation, and correlation of silicon data with simulations, driving performance optimization and cross-functional collaboration across IP and SOC teams.

Qualifications

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of SerDes experience.
• Experience taking high-speed SerDes designs to tape-out and volume production.
• Experience with lab bring-up, characterization, and debugging for production-ready designs.
• Experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm).
• Cross-functional collaboration to deliver IP and SOC integration.
• Strong communication and documentation skills.

Responsibilities

• Define architecture, specifications, and circuit topologies for next-generation SerDes.
• Model system behaviour using MATLAB, SystemVerilog, Verilog-A for link budgets and jitter budgeting.
• Design high-performance analog/mixed-signal circuits in advanced nodes.
• Develop and oversee RX/TX equalization, PLLs, interpolators, DLLs, and TDCs.
• Implement digitally assisted analog circuits and adaptive loops.
• Oversee physical layout to minimize parasitics and process variation impacts.
• Lead lab validation and characterization of SerDes IPs in a state-of-the-art lab.
• Correlate silicon measurements with simulations and optimize performance.

Skills

Tape-out experience

Communication skills

Documentation skills

Education

Master’s degree in Electrical Engineering or related field

PhD in Electrical Engineering or related field

Job description

Principal SerDes Design Engineer

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills