Senior PCIe/CXL Verification Engineer (Subsystem)

Arm; Toronto; Hybrid; CAD 224,000 - 303,000; Full time

Benefits offered by this job

Hybrid working

Accommodations on request

Competitive salary

Job summary

Arm is seeking an experienced verification engineer to verify PCIe and CXL subsystems at the sub-system level. You will craft test plans, develop SystemVerilog/Verilog/UVM testbenches and debug failures, while partnering with RTL designers and architects across the UK, US, Canada and India to drive next‑generation SoCs on leading nodes.

The role offers hybrid working and opportunities to influence verification strategies and methodologies.

Qualifications

• Bachelor's or Master's in Computer Science or Electrical/Computer Engineering or similar field.
• 9+ years in verification of PCIe/CXL subsystems or SoCs.
• Solid understanding of digital hardware design and Verilog HDL.
• Experience in PCIe, CXL and IDE feature verification and performance analysis.
• Knowledge of System Memory Management Unit and GIC Integration with PCIe.
• Experience working with PCIe & CXL IPs and emulation friendly transactors.
• Experience in simulation and emulation platforms.
• Strong debugging experience with debuggers.
• Expertise in UVM-based verification.
• Knowledge of verification strategies like test plan creation, tracking, coverage and sign-off.
• Knowledge of formal methods.

Responsibilities

• Craft test plans and develop SystemVerilog/Verilog/UVM testbenches and tests.
• Debug test failures and issues and drive verification progress.
• Develop and improve verification methodologies used by the team.
• Collaborate with design teams on microarchitecture, verification approaches and performance.
• Balance work with project management activities and guide junior teammates.

Skills

Verilog HDL

SystemVerilog

UVM

PCIe

CXL

Testbench

Performance verification

Emulation

Debugging

RTL verification

Test plan

Education

Bachelor's or Master's in CS/EE

Tools

SystemVerilog simulators

Emulation platforms

Python/Perl scripting

Job description

Arm is seeking an experienced verification engineer to verify PCIe and CXL subsystems at the sub-system level. You will craft test plans, develop SystemVerilog/Verilog/UVM testbenches and debug failures, while partnering with RTL designers and architects across the UK, US, Canada and India to drive next‑generation SoCs on leading nodes.

The role offers hybrid working and opportunities to influence verification strategies and methodologies.