Design Verification Engineer — PCIe & SoC Expert

AMD; Vancouver; On-site; CAD 90,000 - 130,000; Full time

Job summary

AMD is seeking an experienced Design Verification Engineer to join our Vancouver team. You will verify PCIe IP and subsystems using SystemVerilog and UVM, collaborate with architecture, design, and validation teams, and drive verification strategies to ensure silicon success.

The role provides broad exposure to the ASIC development lifecycle, from RTL to signoff, in a fast-paced, collaborative environment with cross-functional teams and state-of-the-art tools.

Qualifications

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

Responsibilities

• Develop, review, and execute comprehensive verification plans to ensure feature and functional coverage.
• Design and implement scalable verification environments using SystemVerilog and UVM.
• Develop reusable verification components, including UVCs, BFMs, models, monitors, and checkers.
• Create, maintain, and execute constrained-random and directed test suites.
• Analyze functional, code, and assertion coverage metrics and drive coverage closure.
• Develop assertions, scoreboards, and other verification infrastructure to improve design quality.
• Debug simulation failures and regression issues to identify root causes and drive resolution.
• Reproduce and analyze silicon-reported functional issues within simulation environments.
• Leverage internal and third-party EDA/CAD tools to support verification development and execution.
• Participate in code reviews and verification signoff activities.
• Collaborate with design, architecture, and validation teams throughout the product development cycle.
• Provide technical leadership by driving verification projects from planning through signoff.

Skills

SystemVerilog/UVM

Verification environments

RTL concepts

ASIC/SoC verification

C/C++/Java

Scripting languages

Simulation tools

PCIe architecture

Processor architectures

On-chip interfaces

Education

Masters or bachelor in electrical or computer engineering

Tools

VCS

Xcelium/NCSIM

Questa

Verdi

Job description

AMD is seeking an experienced Design Verification Engineer to join our Vancouver team. You will verify PCIe IP and subsystems using SystemVerilog and UVM, collaborate with architecture, design, and validation teams, and drive verification strategies to ensure silicon success.

The role provides broad exposure to the ASIC development lifecycle, from RTL to signoff, in a fast-paced, collaborative environment with cross-functional teams and state-of-the-art tools.