Design Verification Engineer - Hybrid; PCIe/SoC Expert

Advanced Micro Devices; Vancouver; Hybrid; CAD 110,000 - 140,000; Full time

Benefits offered by this job

Benefits at a glance

Job summary

AMD is seeking an experienced Design Verification Engineer to verify PCIe IP and subsystems, using SystemVerilog and UVM. You will collaborate with architecture, design, and validation teams to develop verification strategies and drive coverage closure in a fast-paced environment.

The role provides broad exposure to the ASIC development lifecycle from RTL to silicon bring-up, with opportunities to lead verification projects and contribute to first-pass silicon success at AMD.

Qualifications

• Strong SystemVerilog and UVM verification experience.
• Experience with verification environments and testbenches.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC/SoC verification flows.
• Programming in C/C++, Java, or other OO languages.
• Scripting in Perl, Python, Ruby, Shell in Linux/UNIX.
• Familiar with simulators and debugging tools such as VCS, Xcelium/NCSIM, Questa, Verdi.
• Knowledge of PCI Express (PCIe), x86 and ARM architectures.

Responsibilities

• Develop, review, and execute verification plans to ensure feature coverage.
• Design and implement scalable verification environments using SystemVerilog and UVM.
• Develop reusable components, including UVCs, BFMs, models, monitors, and checkers.
• Create constrained-random and directed test suites.
• Analyze coverage metrics and drive closure.
• Develop assertions and scoreboards to improve design quality.
• Debug simulation failures and regression issues to identify root causes.

Skills

SystemVerilog

UVM

C/C++

Verilog HDL

Education

Master's or Bachelor's in Electrical or Computer Engineering

Tools

VCS

Xcelium

NCSIM

Questa

Job description

AMD is seeking an experienced Design Verification Engineer to verify PCIe IP and subsystems, using SystemVerilog and UVM. You will collaborate with architecture, design, and validation teams to develop verification strategies and drive coverage closure in a fast-paced environment.

The role provides broad exposure to the ASIC development lifecycle from RTL to silicon bring-up, with opportunities to lead verification projects and contribute to first-pass silicon success at AMD.