Senior ASIC Verification Engineer

USA Tech Recruit; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Job summary

Confidential Client is seeking a Senior ASIC Verification Engineer to lead verification efforts for a high-performance I/O chiplet. The role focuses on multi-protocol, high-speed interfaces and requires ownership from planning to tape-out.

The candidate will design reusable verification environments, integrate VIPs, and collaborate with RTL, firmware, and IP teams to ensure thorough verification coverage and robust sign-off evidence.

Qualifications

• 10+ years of hands-on ASIC verification experience
• Expertise in SystemVerilog and UVM with constrained-random stimulus
• Experience developing verification plans and coverage strategies
• Hands-on experience with VIP integration, reference modeling, scoreboarding, and assertion-based verification
• Strong understanding of multi-clock designs, reset behavior, protocol corner cases
• Scripting and regression automation skills
• Ability to guide teams and communicate risks clearly
• Experience with silicon bring-up and validation processes

Responsibilities

• Develop verification plans mapping requirements to test scenarios and sign-off criteria
• Design and maintain SystemVerilog/UVM verification environments with sequences, agents, scoreboards, and assertions
• Integrate VIP and verification models to validate IP and end-to-end connectivity
• Verify static-switch mappings, protocol modes, data integrity, latency and throughput
• Verify CSR access, boot/config sequences, interrupts, and error handling with firmware
• Apply simulation, formal verification, and hardware/software co-simulation as appropriate
• Automate regressions, triage failures, and drive coverage through closure
• Review CDC/RDC findings and support gate-level sanity checks
• Support silicon bring-up and debug issues during hardware validation
• Communicate verification readiness and risks to engineering stakeholders

Skills

SystemVerilog

UVM

Verification plans

Constrained-random

Scoreboarding

VIP integration

Regression automation

Debugging

Multi-clock designs

Tools

VIP integration

Reference modeling

Scoreboarding

Assertions (SVA)

Job description

A specialist engineering consultancy supporting advanced ASIC, FPGA, and embedded systems development is partnering with a global technology company developing high-performance silicon for next-generation connectivity and networking applications.

We are looking for a Senior ASIC Verification Engineer to join a long-term client engagement focused on an advanced I/O chiplet combining die-to-die connectivity with multi-protocol, high-speed I/O. The technology brings together interfaces including UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem.

You will collaborate closely with architecture, RTL, verification, firmware, physical design, and IP teams to establish and execute verification strategies for complex silicon. The role spans high-speed datapaths and firmware-controlled management functions, with ownership extending from verification planning through closure, sign-off, and tape-out.

Client identity and detailed program specifications will be shared confidentially during the interview process.

Key Responsibilities:

• Develop comprehensive verification plans mapping requirements to test scenarios, verification platforms, coverage goals, and sign-off criteria.
• Design and maintain reusable SystemVerilog/UVM verification environments, including sequences, agents, scoreboards, reference models, and assertions.
• Integrate vendor VIP and verification models to validate configured IP and end-to-end connectivity across protocol and PHY interfaces.
• Verify static-switch mappings, protocol modes, data integrity, latency, throughput, reset behavior, and recovery mechanisms.
• Verify CSR access, boot and configuration sequences, sideband management, interrupts, and error-handling in collaboration with firmware teams.
• Apply simulation, formal verification, connectivity checks, low-power verification, and hardware/software co-simulation where appropriate.
• Automate regressions, triage failures, and drive functional, assertion, and code coverage through closure, including documenting justified exclusions.
• Review CDC/RDC findings with RTL designers and support gate-level sanity checks.
• Support silicon bring-up and debug issues identified during hardware validation.
• Communicate verification readiness, remaining technical risks, coverage status, and sign-off evidence clearly to engineering stakeholders.

Key Qualifications:

• 10+ years of hands-on ASIC verification experience, including ownership through verification closure, sign-off, and tape-out.
• Strong expertise in SystemVerilog and UVM, including constrained-random stimulus and reusable testbench architecture.
• Proven experience developing verification plans, defining coverage strategies, debugging complex failures, and driving verification closure.
• Hands-on experience with VIP integration, reference modeling, scoreboarding, and assertion-based verification.
• Strong understanding of multi-clock designs, reset behavior, protocol corner cases, and the limitations of simulation and static verification approaches.
• Strong scripting and regression automation skills, with disciplined test and configuration management practices.
• Ability to work independently, provide technical guidance and review others' work, and clearly communicate verification risks and sign-off evidence.
• Strong cross-functional communication skills and experience working with RTL, architecture, firmware, IP, and physical design teams.

Nice to Have:

• Experience with UCIe, PCIe Gen6/Gen7, Ethernet PCS/FEC, 224G SerDes, or mixed-signal IP verification.
• Experience with formal model checking, connectivity verification, or power-aware simulation using UPF.
• Embedded processor verification experience, including secure boot, AXI/APB, register models, or firmware-driven testing.
• Experience with FPGA prototyping, emulation, or silicon bring-up.
• Experience using AI-assisted verification workflows within a controlled engineering and review process.

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