Senior PCIe & SoC Design Engineer

Arm; Toronto; Hybrid; CAD 159,000 - 216,000; Full time

Benefits offered by this job

RSUs

RRSP matching

Generous PTO

Hybrid work

Job summary

Arm Toronto Design Center seeks a senior design engineer with deep expertise in micro-architecture, RTL development and IP integration for complex SoCs. You will drive architecture reviews, write micro-architecture specs, and deliver robust RTL while collaborating with verification and performance teams to optimize system impact.

This hybrid role in Toronto offers engagement with PCIe, CXL and other IPs, while mentoring peers and contributing to design methodologies and schedules.

Qualifications

• Bachelor's or Master's degree in CS/EE or related field.
• 10+ years in design of complex compute subsystems or SoCs.
• Strong knowledge of digital hardware design and Verilog HDL.
• Experience developing and integrating subsystems for PCIe, CXL, UCIe, Ethernet.

Responsibilities

• Write micro-architecture specifications and develop the RTL for SoCs.
• Fix design bugs and run various design checks.
• Collaborate with the verification team to review test plans and debug build issues.
• Partner with performance analysis to evaluate and improve system performance.
• Work with backend implementation on floor planning, constraints, and timing closure.
• Contribute to evolving design methodologies used by the team.
• Guide and support teammates to complete project activities smoothly.
• Balance tasks with Project Management on plans and schedules.

Skills

Micro-architecture

RTL design

PCIe integration

CXL integration

ARM IPs

Verilog HDL

SoC development

Perl

Python

Team mentorship

Education

Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering or related field

Tools

Perl

Python

Job description

Arm Toronto Design Center seeks a senior design engineer with deep expertise in micro-architecture, RTL development and IP integration for complex SoCs. You will drive architecture reviews, write micro-architecture specs, and deliver robust RTL while collaborating with verification and performance teams to optimize system impact.

This hybrid role in Toronto offers engagement with PCIe, CXL and other IPs, while mentoring peers and contributing to design methodologies and schedules.