Senior I/O Chiplet Verification Engineer (SystemVerilog/UVM)

btadesignservices; Ottawa; Hybrid; CAD 120,000 - 150,000; Full time

Job summary

BTADesignServices in Ottawa, Canada, is seeking a Senior I/O Chiplet Verification Engineer to lead verification of high-speed chiplet interfaces and die-to-die interconnects.

You will design verification plans, develop SystemVerilog/UVM environments, and collaborate with architecture, RTL, firmware, and IP partners to achieve sign-off with thorough coverage across protocols and reset/latency requirements.

Qualifications

• 10+ years ASIC verification experience with ownership through tape-out.
• Strong SystemVerilog and UVM skills with constrained-random stimulus.
• Ability to write verification plans, define coverage, debug failures, drive closure.
• Experience verifying high-speed interfaces and die-to-die interconnect.
• VIP integration, reference modeling, scoreboarding, and assertion-based verification.

Responsibilities

• Build verification plans mapping requirements to test scenarios and sign-off criteria.
• Develop reusable SystemVerilog/UVM environments, sequences, agents, and scoreboards.
• Integrate vendor VIP and models, verify IP and end-to-end connectivity.
• Verify high-speed datapaths, protocol modes, data integrity and latency.
• Verify CSR access, boot/config sequences, interrupts and error handling with firmware teams.
• Apply simulation, formal checks, low-power verification, and co-simulation as needed.
• Automate regressions, triage failures, and document exclusions.
• Review CDC/RDC findings, support gate-level bring-up, report readiness.

Skills

ASIC verification

SystemVerilog

UVM

Verification planning

Debug complex failures

Tools

VIP integration

Reference modeling

Scoreboarding

Assertion-based verification

Job description

BTADesignServices in Ottawa, Canada, is seeking a Senior I/O Chiplet Verification Engineer to lead verification of high-speed chiplet interfaces and die-to-die interconnects.

You will design verification plans, develop SystemVerilog/UVM environments, and collaborate with architecture, RTL, firmware, and IP partners to achieve sign-off with thorough coverage across protocols and reset/latency requirements.