Senior Digital Design & Verification Engineer

Semtech; Burlington; On-site; CAD 115,000 - 130,000; Full time

Job summary

Semtech in Burlington, ON seeks an experienced Digital Design verification engineer to help define, verify, and implement advanced digital subsystems within mixed‑signal ICs. You will work in a collaborative team spanning digital, analog, and physical design to meet customer and performance goals.

You will lead verification tasks, mentor engineers, and drive best practices while staying current with state‑of‑the‑art verification methods.

Qualifications

• Requires a B.Sc. in Electrical or Computer Engineering.
• 5+ years of industry experience in verification.
• Proficient with constrained random verification methods.
• Strong SystemVerilog and scripting (Python/TCL/Perl/C).

Responsibilities

• Functional verification of high-speed digital circuits using constrained random verification.
• Behavioral modeling of analog circuits and mixed level simulation.
• Create product and technical documents.
• Prepare project plans and schedules.
• Provide technical guidance of verification tasks within a project team.
• Collaborate with analog, system engineers and marketing to meet requirements.
• Support validation and qualification of end product with other teams.
• Provide leadership, mentoring to other engineers.
• Continual improvement of verification methodology and productivity.

Skills

Constrained random verification

UVM/OVM/AVM/VMM

SystemVerilog

Scripting languages

Unix/Linux

Digital verification

Communication skills

Education

B.Sc. in Electrical or Computer Engineering

Job description

Semtech in Burlington, ON seeks an experienced Digital Design verification engineer to help define, verify, and implement advanced digital subsystems within mixed‑signal ICs. You will work in a collaborative team spanning digital, analog, and physical design to meet customer and performance goals.

You will lead verification tasks, mentor engineers, and drive best practices while staying current with state‑of‑the‑art verification methods.