Design Verification Engineer

TetriQ Solutions PVT LTD; Vancouver; Hybrid; CAD 90,000 - 120,000; Full time

Job summary

TetriQ Solutions PVT LTD in Vancouver, BC is seeking a Design Verification Engineer with strong ASIC/SoC verification background to develop and execute verification environments and ensure high-quality digital designs.

The role focuses on building testbenches in SystemVerilog/UVM, running functional and regression tests, and driving coverage closure, with opportunities to work on AMBA/AXI, PCIe, and Ethernet protocols.

Qualifications

• SystemVerilog and UVM expertise required.
• Strong RTL and digital design knowledge for ASIC/SoC verification.
• Degree in Electrical/ Electronics/ Computer Engineering required.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyze functional and code coverage and drive closure.
• Debug RTL and simulation failures with design teams.
• Verify peripherals such as AMBA/AXI, PCIe, Ethernet.
• Automate regression and testing using Python, Perl, or shell scripting.

Skills

SystemVerilog & UVM

RTL & digital design

ASIC/SoC verification

Debugging skills

Scripting skills

Education

Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering

Tools

VCS

Xcelium

Questa

Job description

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Summary

We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyze functional/code coverage and drive coverage closure.
• Debug RTL and simulation failures and work with design teams to resolve issues.
• Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
• Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills

• Strong SystemVerilog & UVM experience.
• Solid understanding of RTL, digital design, and ASIC/SoC verification.
• Experience with simulation tools such as VCS, Xcelium, or Questa.
• Strong debugging and scripting skills.
• Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.