Senior ASIC Verification Engineer - Drive Formal & Coverage

Ciena Corporation; Ottawa; On-site; CAD 109,000 - 174,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) & DCPP with company matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company-paid holidays

Paid sick leave

Vacation time

Paid Family Leave

Job summary

Ciena Corporation in Ottawa, Canada, is seeking a hardworking digital verification engineer to join a team of digital design engineers, verification engineers and architects to verify the Wavelogic family of products.

You will propose and implement innovative verification strategies, build verification environments using SystemVerilog UVM and/or C, and perform coverage and formal verification while aligning with architecture and requirements.

Qualifications

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level.
• Highly motivated self-starter able to work independently while being a great teammate.
• Ability to methodically tackle sophisticated technical problems.
• Excellent organization, written and oral (English) interpersonal skills.
• Familiarity with formal verification methods.
• Familiarity with standards and protocols such as OTN, B100G, Ethernet.
• Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, SystemC.

Responsibilities

• Propose and implement innovative verification strategies to thoroughly simulate and validate functional blocks and subsystems.
• Read and understand architecture and functional requirements specifications; collaborate with systems engineers and architects.
• Create testbench environment and components, agents, scoreboard; develop test scenarios for architectural blocks using SystemVerilog UVM and/or C.
• Perform coverage driven verification and formal verification; monitor regressions and debug failures with the designers.
• Report status updates on a regular basis.

Skills

SystemVerilog UVM

Python

C/C++

SystemC

Problem solving

Team collaboration

English communication

Education

BEng/BSc or MEng/MSc in Electrical or Computer Engineering, Computer Science or related field

Tools

UVM Testbenches

Job description

Ciena Corporation in Ottawa, Canada, is seeking a hardworking digital verification engineer to join a team of digital design engineers, verification engineers and architects to verify the Wavelogic family of products.

You will propose and implement innovative verification strategies, build verification environments using SystemVerilog UVM and/or C, and perform coverage and formal verification while aligning with architecture and requirements.