Senior ASIC Verification Engineer, onsite Kanata

Ciena Corporation; Ottawa; Presencial; CAD 109.000 - 174.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, and vision plans

401(K) & DCPP with company matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company-paid holidays

Paid sick leave

Vacation time

Paid Family Leave

Descripción de la vacante

Ciena Corporation in Ottawa, Canada, is seeking a hardworking digital verification engineer to join a team of digital design engineers, verification engineers and architects to verify the Wavelogic family of products.

You will propose and implement innovative verification strategies, build verification environments using SystemVerilog UVM and/or C, and perform coverage and formal verification while aligning with architecture and requirements.

Formación

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level.
• Highly motivated self-starter able to work independently while being a great teammate.
• Ability to methodically tackle sophisticated technical problems.
• Excellent organization, written and oral (English) interpersonal skills.
• Familiarity with formal verification methods.
• Familiarity with standards and protocols such as OTN, B100G, Ethernet.
• Familiarity with programming languages such as Python, Make, bash, object-oriented programming, C, C++, SystemC.

Responsabilidades

• Propose and implement innovative verification strategies to thoroughly simulate and validate functional blocks and subsystems.
• Read and understand architecture and functional requirements specifications; collaborate with systems engineers and architects.
• Create testbench environment and components, agents, scoreboard; develop test scenarios for architectural blocks using SystemVerilog UVM and/or C.
• Perform coverage driven verification and formal verification; monitor regressions and debug failures with the designers.
• Report status updates on a regular basis.

Conocimientos

SystemVerilog UVM

Python

C/C++

SystemC

Problem solving

Team collaboration

English communication

Educación

BEng/BSc or MEng/MSc in Electrical or Computer Engineering, Computer Science or related field

Herramientas

UVM Testbenches

Descripción del empleo

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being—on and off the job. Connect with a career that matters.

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry.

To further strengthen our team, we are looking for a hardworking digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects.

Your role as a digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products. As a digital verification engineer, you are encouraged to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects. You are held responsible for the complete and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods. You are encouraged the build the verification, functional coverage and formal verification test plans. You are accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable. You will perform coverage driven verification, formal verification, monitor regressions and debug resulting failures with the help of the function's designer. Reporting status updates on a regular basis.

The Must Haves:

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically tackle sophisticated technical problems
• Excellent organization, written and oral (English) interpersonal skills
• Familiarity with formal verification methods
• Familiarity with standards and protocols such as OTN, B100G, Ethernet
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

Pay Range

The annual salary range for this position is $109,000 - $174,000 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.

• medical, dental, and vision plans
• participation in 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation time
• Paid Family Leave and other leaves of absence

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.