High-Speed Optical DSP Engineer

Celero Communications, Inc.; Ottawa; On-site; CAD 90,000 - 130,000; Full time

Job summary

Celero Communications Inc. is seeking an Optical Design Engineer specializing in DSP for high-speed optical transceivers. The role combines algorithm development, system-level modeling, and collaboration with ASIC, firmware, and verification teams to ensure silicon-ready implementations.

The ideal candidate will hold a Master’s or Ph.D. in a relevant field, have 2+ years of industry experience, and be proficient in C/C++, Python, and MATLAB.

Qualifications

• Strong theoretical background in DSP, digital communications, and fiber-optic systems.
• Experience developing DSP algorithms for high-speed communications.
• Minimum two years of industry experience.

Responsibilities

• Research, develop, and evaluate DSP algorithms for high-speed optical communication systems.
• Design and optimize DSP blocks used in optical transceivers, including adaptive equalization, timing recovery, carrier phase recovery, polarization demultiplexing, and nonlinear compensation.
• Develop system-level simulation models of optical communication links and evaluate DSP algorithm performance under realistic channel conditions.
• Analyze performance under various impairments such as noise, chromatic dispersion, polarization effects, and hardware non-idealities.
• Verify and optimize algorithm performance through floating-point and fixed-point simulations.
• Develop bit-accurate and cycle-accurate models to support ASIC implementation.
• Document design details and collaborate with ASIC, firmware, and verification teams to ensure reliable implementation in silicon.

Skills

DSP design

Digital communications

C/C++

Python

MATLAB

System modeling

Education

Master’s or Ph.D. in Electrical Engineering, Physics, or Mathematics

Tools

GitHub

Verilog

VHDL

Job description

Celero Communications Inc. is seeking an Optical Design Engineer specializing in DSP for high-speed optical transceivers. The role combines algorithm development, system-level modeling, and collaboration with ASIC, firmware, and verification teams to ensure silicon-ready implementations.

The ideal candidate will hold a Master’s or Ph.D. in a relevant field, have 2+ years of industry experience, and be proficient in C/C++, Python, and MATLAB.