Senior ASIC Design Engineer — DSP, SerDes & Optics

Celero Communications, Inc.; Ottawa; On-site; CAD 110,000 - 150,000; Full time

Job summary

Celero Communications is seeking an experienced ASIC Design Engineer to join our fast-growing semiconductor startup in Ottawa. You will design and implement high-performance digital circuits and ASIC blocks using Verilog/SystemVerilog, with exposure to DSP, SerDes, and mixed-signal interfaces.

You will collaborate with Analog, Verification, and Physical Design teams, perform synthesis and timing analysis, develop automation scripts in Python or Tcl, and help drive silicon bring-up from RTL

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering, Computer Engineering, or a related field.
• 5+ years of digital ASIC design with ownership of complex blocks or subsystems.
• Strong proficiency in Verilog and SystemVerilog.
• Solid understanding of RTL design, digital design principles, and ASIC development methodologies.
• Experience with ASIC design flows and industry-standard EDA tools.
• Familiarity with DSP, SerDes, analog/mixed-signal concepts and high-speed interfaces.

Responsibilities

• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to integrate mixed-signal ASICs.
• Develop and optimize data paths, signal processing blocks, and control logic for optical systems.
• Perform synthesis, timing analysis, lint, formal verification, CDC, and signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Conduct RTL simulation and debugging to validate functionality.
• Support block-level and top-level integration and silicon bring-up.
• Participate in architecture/design reviews and provide guidance to engineers.
• Develop scripts/automation using Python, Tcl, or similar languages to improve efficiency.

Skills

Verilog/SystemVerilog

RTL design

Synthesis/Timing

Python/Tcl scripting

DSP/SerDes knowledge

Communication skills

Education

Bachelor’s or higher degree in Electrical/Computer Engineering

Tools

EDA tools

Job description

Celero Communications is seeking an experienced ASIC Design Engineer to join our fast-growing semiconductor startup in Ottawa. You will design and implement high-performance digital circuits and ASIC blocks using Verilog/SystemVerilog, with exposure to DSP, SerDes, and mixed-signal interfaces.

You will collaborate with Analog, Verification, and Physical Design teams, perform synthesis and timing analysis, develop automation scripts in Python or Tcl, and help drive silicon bring-up from RTL