Lead ASIC/FPGA Verification Architect

Qualcomm; Ottawa; Hybrid; CAD 120,000 - 190,000; Full time

Job summary

Qualcomm Canada ULC in Ottawa is seeking an experienced ASIC Engineer to define, model, design, verify, and document IP for high-performance, low-power products. You will collaborate across teams to map execution paths for PCIe Gen7 and CXL 4.0.

Candidates bring advanced degrees and 7+ years of ASIC/FPGA experience, strong SystemVerilog/UVM skills, and the ability to mentor junior engineers. The role emphasizes innovation, rigorous verification, and contribution to next-generation silicon.

Qualifications

• Bachelor’s degree with 6+ years ASIC/FPGA work experience.
• Master’s degree with 5+ years ASIC/FPGA work experience.
• PhD with 4+ years ASIC/FPGA work experience.
• Strong knowledge of PCIe, CXL, Ethernet protocols and related design.

Responsibilities

• Deliver IP blocks/subsystems for PCIe Gen7 and CXL 4.0 in FPGAs or ASICs.
• Lead ASIC or FPGA projects.
• Lead verification of IP blocks/subsystems.
• Streamline ASIC development with advanced tools and AI-based approaches.
• Develop verification test plans.
• Architect, develop and document verification environments with SystemVerilog and UVM.
• Develop and debug test cases against RTL to complete the test plan.
• Mentor junior engineers.

Skills

PCIe

CXL

UALink

Ethernet

SystemVerilog

UVM

Constrained Random

Simulation Tools

Shell Scripting

Version Control

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Siemens VIP

Cadence VIP

Synopsys VIP

AI-based verification tools

Job description

Qualcomm Canada ULC in Ottawa is seeking an experienced ASIC Engineer to define, model, design, verify, and document IP for high-performance, low-power products. You will collaborate across teams to map execution paths for PCIe Gen7 and CXL 4.0.

Candidates bring advanced degrees and 7+ years of ASIC/FPGA experience, strong SystemVerilog/UVM skills, and the ability to mentor junior engineers. The role emphasizes innovation, rigorous verification, and contribution to next-generation silicon.