ASIC Verification Engineer (33722)

Myticas Consulting; Ottawa; On-site; CAD 110,000 - 170,000; Full time

Job summary

Myticas Consulting is seeking a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse environment. The role focuses on building verification infrastructure and creating UVM-based generators and checkers.

You will lead test plan development, execute verification strategies, and drive self-checking tests for complex ASIC designs, leveraging SystemVerilog, Python, and formal tools in a distributed team setting.

Qualifications

• Bachelor’s degree in computer science or electrical engineering (master’s preferred).
• 8+ years of experience in ASIC verification.
• Proven experience in developing and implementing test plans at block or sub-chip levels.
• Proficiency in SystemVerilog and scripting languages such as Python.
• Deep understanding of UVM methodology.
• Experience with assertions, functional coverage, code coverage, and formal verification tools.
• Strong communication skills and ability to work effectively in a distributed team.

Responsibilities

• Lead the development of verification infrastructure for advanced ASIC designs.
• Create SystemVerilog/UVM-based protocol and traffic generators/checkers.
• Develop and execute test plans based on functional and standards requirements.
• Define, develop, and run self-checking tests for complex digital ASICs.

Skills

SystemVerilog

UVM

Python

Test plans

Assertions

Functional/Code coverage

Formal verification tools

Education

Bachelor’s degree in CS or Electrical Engineering

Master’s degree preferred

Tools

Regression/Verification environment

Job description

Our client is seeking a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse environment.

Key Responsibilities

• Lead the development of verification infrastructure for advanced ASIC designs
• Create System Verilog/UVM-based protocol and traffic generators/checkers
• Develop and execute test plans based on functional and standards requirements
• Define, develop, and run self-checking tests for complex digital ASICs

Required Qualifications

• Bachelor’s degree in computer science or electrical engineering (master’s preferred)
• 8+ years of experience in ASIC verification
• Proven experience in developing and implementing test plans at block or sub-chip levels
• Proficiency in System Verilog and scripting languages such as Python
• Deep understanding of UVM methodology
• Experience with assertions, functional coverage, code coverage, and formal verification tools
• Strong communication skills and ability to work effectively in a distributed team

Preferred Skills

• Knowledge of DSP and/or FEC technologies