IP Verification Engineer

Advanced Micro Devices; Markham; Hybrid; CAD 110,000 - 150,000; Full time

Job summary

AMD in Markham, Ontario is seeking a Verification Engineer in the AECG Group to verify FPGA/ASIC IP, collaborate with architecture, IP design, PD, and product engineers for first pass silicon success.

You will write UVM-based testbenches, develop test plans, and run regressions while maintaining strong collaboration across sites and time zones. Hybrid work model with ongoing learning opportunities.

Qualifications

• Proficient in IP level ASIC verification.
• Expert in Verilog, System Verilog, Object Oriented programming.
• Expert in developing UVM based verification frameworks and testbenches.
• Scripting and automation of verification processes and flows.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Good Computer Architecture, systems knowledge.
• Comfortable in python / perl and editing / maintaining scripts.
• Exposure to leadership or mentorship is an asset.
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out.
• Experience with PCIe, CXL, NVMe or ethernet protocols.
• Strong communication skills and the ability to work independently as well as in a cross-site team environment.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

Skills

Verilog

SystemVerilog

UVM

Python

Perl

PCIe

CXL

NVMe

OO programming

Education

Bachelor's or Master's in Computer or Electrical Engineering

Tools

UVM-based verification frameworks

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE:

As a verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.

THE PERSON:

You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBLITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
• Build the directed and random verification tests
• Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Expert in Verilog, System Verilog, Object Oriented programming
• Expert in developing UVM based verification frameworks and testbenches
• Scripting and automation of verification processes and flows
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Good Computer Architecture, systems knowledge
• Comfortable in python / perl and editing / maintaining scripts
• Exposure to leadership or mentorship is an asset
• Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
• Experience with PCIe, CXL, NVMe or ethernet protocols
• Strong communication skills and the ability to work independently as well as in a cross-site team environment

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-EV1

#LI-HYBRID

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.