Senior Process Engineer (Advanced Packaging – 2.5D/3D Integration)

STATS CHIPPAC MANAGEMENT PTE. LTD.; Região Norte; Presencial; BRL 180 000 - 270 000; Tempo integral

Resumo da oferta

STATS CHIPPAC MANAGEMENT PTE. LTD. seeks an expert Senior Process Engineer to drive process development, characterization, and mass production scale-up for wafer assembly steps such as back grinding, dicing, laser groove, edge trimming, lamination in our 2.5D/3D packaging research lab.

You will optimize thinning, grinding, laser cutting, and edge-relieving processes; evaluate compatibility with bumping and flip-chip; and document SOPs, WI, and CAPA for ramp-up and production release.

Qualificações

• Bachelor or Master degree in Materials Science, Chemical/Mechanical Engineering, Microelectronics, or a related technical discipline.

Responsabilidades

• Develop and optimize wafer backside grinding/thinning, laser stealth dicing, edge trimming, and lamination in R&D and production lines.
• Characterize wafer thickness uniformity, cutting quality, and production capacity; drive continuous process optimization for higher yield.
• Develop new DBG/SDBG processes for ultra-thin wafers with detailed process characterization.
• Evaluate compatibility with bumping/flip-chip; optimize process integration to prevent front-end related failures.
• Compile SOPs, work instructions, failure reports, and change documents; support ramp-up and process verification.

Conhecimentos

Process engineering

Data-driven problem solving

DOE

SPC

FMEA

Cross-functional leadership

Mentoring

Formação académica

Bachelor or Master degree in Materials Science or related field

Ferramentas

DISCO

Tokyo Seimitsu

ACCRETECH

JMP

Minitab

Descrição da oferta de emprego

About the role

We are seeking an expert Senior Process Engineer to focus on process development, characterization, and mass production scale-up for wafer assembly process steps such as back grinding, dicing, laser groove, edge trimming, lamination etc, in our advanced 2.5D/3D packaging research lab. In this technical role, your primary objective will be developing and delivering ultra-thin, high yield, high strength diced dies for 2.5D/3D advanced packaging.

Key responsibilities

• Responsible for process development for Si/mold wafer backside grinding/thinning process, laser stealth dicing process, edge trimming process and lamination process for functional chips, with our R&D line.

• Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, and edge chipping for the Si wafers.

• Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.

• Characterize wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.

• New process development for DBG or SDBG process for super thin wafers processing with detailed process characterization.

• Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.

• Compile process SOP, WI, failure reports and engineering change documents; support ramp up process setup and process verification.

About you

• Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline

• 5+ years of hands-on process engineering experience inside an advanced packaging foundry, OSAT, or leading-edge semiconductor fab focusing specifically on 2.5D, 3D, HBM, or Chiplet architectures.

• 3 to 6+ years of hands-on process engineering in wafer mounting, wafer dicing, wafer thinning or grinding, especially in handling advanced packaging wafers with more complex topology or stack

• Deep operational and theoretical expertise in advanced backend toolsets (e.g., DISCO, Tokyo Seimitsu/ACCRETECH). Direct experience with ultra-thin wafer handling, carrier tape management, and sub-surface damage control.

• Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production

• Proficient in Design of Experiments (DOE), Statistical Process Control (SPC), and Failure Mode and Effects Analysis (FMEA) using advanced data analytics platforms like JMP or Minitab.

• Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods

• Exceptional cross-functional leadership capabilities, data-driven structured problem-solving (8D, fishbone, 5-Whys), and a track record of mentoring junior engineers and packaging technicians.