PhD: QoS-Driven Shared Memory Chiplet Architectures

IMEC; Belgique; Sur place; EUR 28 000 - 36 000; Plein temps

Résumé du poste

Imec Heilbronn is seeking a PhD researcher to investigate shared memory chiplet architectures that provide scalability and predictable performance for safety-critical systems. The work will explore cross-layer QoS mechanisms across interconnects, memory hierarchies, and scheduling to guarantee bounded latency.

You will contribute to designing die-to-die communication and chiplet memory controllers with differentiable service levels, bridging research and potential industrial adoption in

Qualifications

• Master's degree in electrical engineering, computer science, or related field is required.
• Solid foundation in processor, compute systems and chiplet architecture is expected.
• Experience with hardware description languages is beneficial.

Responsabilités

• Develop architectural principles for predictable access to shared memory chiplets.
• Investigate die-to-die communication mechanisms with QoS enforcement.
• Design memory schedulers and chiplet memory controllers for fairness and isolation.
• Validate proposals through system-level simulations and performance metrics.

Connaissances

Processor architecture

Chiplet systems

Compute systems

Formation

Masters degree in electrical engineering, computer science, or related field

Outils

VHDL

Verilog

SystemVerilog

Description du poste

Imec Heilbronn is seeking a PhD researcher to investigate shared memory chiplet architectures that provide scalability and predictable performance for safety-critical systems. The work will explore cross-layer QoS mechanisms across interconnects, memory hierarchies, and scheduling to guarantee bounded latency.

You will contribute to designing die-to-die communication and chiplet memory controllers with differentiable service levels, bridging research and potential industrial adoption in