System-Level Reliability Architect for Compute Systems

Imec India Private Limited; Belgique; À distance; EUR 90 000 - 120 000; Plein temps

Résumé du poste

imec is seeking a System-Level Reliability Researcher in Leuven, Belgium. You will develop methodologies to translate hardware faults into architectural models and system-level metrics, collaborating across technology, circuits, and design teams to influence resilient compute architectures.

The role emphasizes reliability modeling, simulation, and quantitative analysis, with a focus on SIL and lifetime-related degradation, and it offers opportunities to publish and advance research across CSA

Qualifications

• Master's or PhD in Electrical/Electronics/Computer Engineering/Science.

Responsabilités

• Develop system-level reliability assessment methods for processors, accelerators, memory subsystems, SoCs, and chiplet-based architectures.
• Create architectural fault models and abstractions from lower-layer reliability data.
• Build and use simulation, emulation, and fault-injection frameworks to study fault propagation and impact.
• Quantify reliability outcomes like Silent Data Corruption, errors, availability loss and degradation.
• Evaluate Reliability, Availability, and Serviceability (RAS) mechanisms and techniques.
• Study workload-dependent reliability under realistic operating profiles.
• Link technology-level fault characteristics to system-level models for design decisions.
• Collaborate with CSA teams and external partners; contribute to publications.

Connaissances

System-level reliability

Compute system architecture

RAS concepts

Fault tolerance

Error detection

Experiment design

Collaboration across domains

Analytical & quantitative skills

Mentoring/leadership

Formation

Master's or PhD in Electrical/Electronics/CS/Science

Outils

Architectural simulators

Fault-injection frameworks

Description du poste

imec is seeking a System-Level Reliability Researcher in Leuven, Belgium. You will develop methodologies to translate hardware faults into architectural models and system-level metrics, collaborating across technology, circuits, and design teams to influence resilient compute architectures.

The role emphasizes reliability modeling, simulation, and quantitative analysis, with a focus on SIL and lifetime-related degradation, and it offers opportunities to publish and advance research across CSA