Senior CPU Subsystem RTL & Verification Engineer

Imec; Vlaams-Brabant; Remote; EUR 90,000 - 120,000; Full time

Job summary

Imec in Leuven, Belgium, is seeking a Digital Designer to own RTL design of CPU-subsystem blocks and drive verification from unit tests to subsystem integration. The role focuses on SystemVerilog RTL, RISC-V cores, and integration with caches and interconnects.

You will collaborate with multidisciplinary teams across the platform, prototypes and physical-aware design groups, and contribute to tape-out readiness while addressing PPA and timing implications.

Qualifications

• At least 5 years of RTL design experience in SystemVerilog/Verilog for CPU or similar subsystems.
• Solid grasp of CPU microarchitecture and how to translate specs into RTL.
• Strong functional verification capability: UVM, SVA, coverage-driven methods.
• Familiar with AXI/CHI/TileLink interconnects at RTL and verification levels.
• Hands-on with industry EDA flows for simulation, lint, CDC, and synthesis.
• Scripting proficiency (Python, Tcl, Make) for automation and integration.
• Excellent written and spoken English; collaborative, multidisciplinary work.
• Assets: RISC‑V cores, formal verification, HLS, sub‑5nm or chiplet experience.

Responsibilities

• Translate microarchitectural specs into RTL (SystemVerilog) for CPU subsystem blocks.
• Integrate RISC‑V cores with caches, coherency, AXI/CHI interconnects, and debug/trace.
• Develop and execute functional verification environments (testbenches, UVM, SVA, coverage).
• Collaborate with SoC and chiplet architects to refine specifications and implementations.
• Anticipate PPA and floorplan implications in RTL, supporting physical-aware design iterations.
• Contribute to verification IP, regression infrastructure, and design/verification flow improvements.
• Document design and verification intent clearly for future engineers.
• This is a temporary contract of two years, with the possibility to extend.

Skills

RTL design

SystemVerilog

Verification

UVM

SVA

Constrained-random

Interconnect protocols

Python scripting

English communication

Collaboration

Tools

Synopsys

Cadence

Siemens

Job description

Imec in Leuven, Belgium, is seeking a Digital Designer to own RTL design of CPU-subsystem blocks and drive verification from unit tests to subsystem integration. The role focuses on SystemVerilog RTL, RISC-V cores, and integration with caches and interconnects.

You will collaborate with multidisciplinary teams across the platform, prototypes and physical-aware design groups, and contribute to tape-out readiness while addressing PPA and timing implications.