Hardware Verification Engineer

Baya Systems; Town of Cambridge; On-site; AUD 100,000 - 130,000; Full time

Benefits offered by this job

Comprehensive medical, dental, and vision benefits

401(k) retirement plan

Equity

Job summary

Baya Systems is seeking a Design Verification Engineer based in Town Of Cambridge, Australia. The candidate will be responsible for creating test plans and writing UVM/SystemVerilog code to ensure efficient design verification.

This role demands a BS or MS in related fields and over 8 years of verification experience, ideally with proficiency in Verilog, SystemVerilog, and UVM-based testbenches. The position offers benefits including performance incentives and comprehensive medical coverage.

Qualifications

• 8+ years of hands-on experience in block-level, IP-level, or SoC-level verification.
• Deep experience with UVM-based testbenches.
• Knowledge of ARM AMBA protocols (AXI, APB, AHB) and ARM CHI protocol.

Responsibilities

• Create test plans for configurable IPs providing interconnectivity.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.

Skills

Verilog

SystemVerilog

UVM

Python

ARM AMBA protocols

Education

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science

Tools

EDA tools

Job description

Baya Systems – Design Verification Engineer

England, UK (Bristol, Cambridge, London)

Responsibilities

• Create test plans for highly configurable IPs that provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems.
• Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards.
• Collaborate with software teams to define and implement configurable testbenches.
• Work with design teams on test plans, failure debugging, and coverage analysis.

Qualifications and Preferred Skills

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of hands‑on experience in block‑level, IP‑level, or SoC‑level verification.
• Proficiency in Verilog and SystemVerilog.
• Familiarity with industry‑standard EDA tools for simulation and debugging.
• Deep experience with UVM‑based testbenches.
• Experience with modern programming languages such as Python.
• Knowledge of ARM AMBA protocols (AXI, APB, AHB) and, preferably, ARM CHI protocol.
• Experience working with IPs for caches, cache coherency, memory subsystems, interconnects, and NoCs.
• Knowledge of formal verification techniques and emulation platforms is a plus.
• Excellent problem‑solving skills and attention to detail.
• Strong communication and collaboration skills.

Compensation

• Salary commensurate with experience.
• Performance incentives.
• Comprehensive medical, dental, and vision benefits.
• 401(k) retirement plan.
• Equity.