Senior Digital Design Engineer — RTL/Verilog, DFT & Timing

Infineon; Western Australia; On-site; AUD 110,000 - 170,000; Full time

Job summary

Infineon Technologies Australia seeks an Engineer / Senior Engineer Digital Design to join our R&D team in Western Australia. You will develop RTL, verify digital circuits, and optimize IPs for high performance and low power.

Qualifications include a Bachelor or Master in Electrical Engineering, experience with SystemVerilog/Verilog/VHDL, and familiarity with Cadence or Synopsys tools. Strong English communication and problem-solving skills are essential.

Qualifications

• Bachelor or Master in Electrical Engineering or similar with electronics focus
• Proficiency in SystemVerilog/Verilog/VHDL for RTL design and verification
• Familiar with digital design flow: LEC, Spyglass, synthesis constraints, ATPG, PrimeTime

Responsibilities

• RTL design coding and verification of digital circuits for sensor/IPs
• Run Logic Synthesis and Static Timing Analysis; ensure timing closure
• DFT/power integrity activities: Scan insertion, ATPG, power analysis
• Collaborate with physical designers for timing closure and ECOs
• Support verification and view generation teams to verify IP views

Skills

RTL design

Verilog/SystemVerilog

VHDL

EDA tools

Digital design flow

Timing analysis

IP integration

Education

Bachelor/Masters in Electrical Engineering

Tools

Cadence

Synopsys

Spyglass

Job description

Infineon Technologies Australia seeks an Engineer / Senior Engineer Digital Design to join our R&D team in Western Australia. You will develop RTL, verify digital circuits, and optimize IPs for high performance and low power.

Qualifications include a Bachelor or Master in Electrical Engineering, experience with SystemVerilog/Verilog/VHDL, and familiarity with Cadence or Synopsys tools. Strong English communication and problem-solving skills are essential.