Senior SoC Physical Design Engineer (Ultra-Low Power)

Meta; Redmond; Presencial; AUD 255.000 - 359.000; Jornada completa

Descripción de la vacante

Meta’s Reality Labs Silicon team focuses on AI-enabled wearables. As a Physical Design Engineer, you will collaborate with SoC architects, front-end and back-end hardware designers, and power/performance teams to drive physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes.

You will develop custom methodologies across the physical design cycle—floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and STA—to optimize power,

Formación

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent practical experience.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
• 8+ years of experience in SoC or ASIC physical design.
• Hands-on RTL-to-GDSII in 3nm or below, including floorplanning, physical synthesis, placement, clock-tree synthesis, routing, STA, signoff.
• Experience with low-power techniques: power gating, voltage islands, UPF, DVFS.
• STA with timing constraints, PVT corners/modes, DFT signoff; OCV/POCV and co effects.
• Experience with EDA tools: Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus.
• Scripting in TCL, Python, or Perl; reading Verilog RTL.
• Experience collaborating across RTL, DV, DFx, package, and vendor teams.

Responsabilidades

• Lead physical implementation from floorplanning through tapeout, including ultra-low-power logic synthesis, place-and-route, STA, and EM/IR.
• Define design flows to realize power and timing, meeting perf/watt budgets in wearable form factors.
• Identify and resolve physical bottlenecks related to congestion, timing, and power.
• Develop automation and AI-assisted flows to improve throughput and QoR.
• Collaborate with RTL designers to feed back into microarchitecture for power and area efficiency.
• Work with package engineers to ensure floorplan and power plan meet product requirements.
• Partner with design verification and DFx teams to ensure physical implementation supports gate-level correctness and testability.
• Drive EDA vendor engagement, tool evaluations, and flow improvements.

Conocimientos

RTL to GDSII

Low-power design

Floorplanning

Clock tree synthesis

EDA tools

Scripting (TCL/Python/Perl)

Team collaboration

Educación

Bachelor's degree in Computer Science/Engineering

Master's or PhD in Electrical/Computer Engineering

Herramientas

Fusion Compiler

Genus

ICC2

Innovus

PrimeTime

Tempus

RedHawk

Voltus

Descripción del empleo

Meta’s Reality Labs Silicon team focuses on AI-enabled wearables. As a Physical Design Engineer, you will collaborate with SoC architects, front-end and back-end hardware designers, and power/performance teams to drive physical implementation of IP, subsystems, and the chip top-level in advanced technology nodes.

You will develop custom methodologies across the physical design cycle—floorplanning, physical synthesis, placement, clock-tree synthesis, routing, and STA—to optimize power,