SOC Design Engineer: RTL & IP Integration, Visa Friendly

ARM; Town of Cambridge; In loco; AUD 105.000 - 142.000; Tempo pieno

Vantaggi offerti da questo lavoro

Health and wellness programs

Flexible work-life balance options

Professional development opportunities

Visa sponsorship

Descrizione del lavoro

Arm's Cambridge-based SOC Design Engineer role focuses on developing System on Chips by integrating IP blocks such as CPU clusters, PCIe and memory interfaces. You will draft micro-architecture specs, create RTL designs in Verilog/SystemVerilog, and collaborate with verification to meet timing and power goals.

You will participate in backend tasks like floor planning and timing closure, while contributing to design methodologies and mentoring teammates in a dynamic hardware team.

Competenze

• Proven experience designing and integrating subsystems for PCIe, DDR/LPDDR, HBM, UCIe and Ethernet.
• Expertise in RTL design for complex SoC development using Verilog and/or SystemVerilog.
• Strong skills in static design checks, synthesis, timing analysis and power management.
• Familiarity with all design phases from concept to verification and documentation.
• Ability to produce detailed specifications and scripting support.

Mansioni

• Integrate IP components such as CPU clusters, PCIe, DDR/LPDDR, and other high‑speed IP for SoCs.
• Draft micro-architecture specifications, develop RTL designs, troubleshoot bugs, and run design checks.
• Collaborate with verification to analyze test plans and resolve design issues.
• Assist backend implementation with floor planning, constraints, and timing closure.
• Enhance design methodologies and improve quality standards and inspections.
• Mentor team members and support project planning and scheduling.

Conoscenze

PCIe integration

DDR/LPDDR

HBM

UCIe

Ethernet

RTL design (Verilog/SystemVerilog)

Lint/CDC/RDC checks

Synthesis

Timing analysis

Power management

Shell scripting (Tcl/Perl/Python)

Strumenti

Verilog

SystemVerilog

Tcl

Perl

Python

Descrizione del lavoro

Arm's Cambridge-based SOC Design Engineer role focuses on developing System on Chips by integrating IP blocks such as CPU clusters, PCIe and memory interfaces. You will draft micro-architecture specs, create RTL designs in Verilog/SystemVerilog, and collaborate with verification to meet timing and power goals.

You will participate in backend tasks like floor planning and timing closure, while contributing to design methodologies and mentoring teammates in a dynamic hardware team.