Senior SoC Digital Design Engineer — Low-Power ASICs

Meta; Redmond; Vor Ort; AUD 209.000 - 299.000; Vollzeit

Benefits dieser Stelle

Bonus

Equity

Benefits

Zusammenfassung

Meta is seeking a Digital Design Engineer to help design ASIC digital µArchitecture, RTL, and micro-architecture for production silicon. You will collaborate with researchers and engineers to map algorithms onto hardware and specify IP/subsystem integration requirements.

Work with DV, PD, and architecture teams to meet power and performance targets while leveraging AI tools to optimize workflows and drive measurable impact. Equity and benefits are offered.

Qualifikationen

• Bachelor's degree in CS/CE or equivalent practical experience.
• 6+ years hardware design experience for production silicon.
• Experience in digital design architecture, RTL coding, and micro-architecture development.
• Ability to communicate design decisions to cross-functional partners.

Aufgaben

• Contribute to ASIC digital µArchitecture and design.
• Assist in performance/power analysis to meet targets.
• Map algorithms onto hardware and specify IP/subsystem integration requirements.
• Collaborate with Verification, Physical Design, and Design for Test teams.
• Develop micro-architecture, RTL coding, and design verification for IPs.
• Drive IP/sub-system micro-architecture and RTL design with DV and PD leads.

Kenntnisse

Digital design

RTL coding

Micro-architecture

Cross-functional communication

Ausbildung

Bachelor's degree in Computer Science/Engineering

Tools

HDL design tools

Jobbeschreibung

Meta is seeking a Digital Design Engineer to help design ASIC digital µArchitecture, RTL, and micro-architecture for production silicon. You will collaborate with researchers and engineers to map algorithms onto hardware and specify IP/subsystem integration requirements.

Work with DV, PD, and architecture teams to meet power and performance targets while leveraging AI tools to optimize workflows and drive measurable impact. Equity and benefits are offered.