Memory Architect, Subsystem for Wearable AI Chips

Meta; Redmond; On-site; AUD 166,000 - 250,000; Full time

Job summary

Meta Reality Labs is seeking a Memory Architect on the Subsystem Architecture team to drive on-chip memory design for wearable AR/AI enabled chips. You will collaborate with senior memory architects to balance caches, scratchpads, SRAM and memory hierarchy within tight wearable budgets.

The role requires 2+ years in memory-focused silicon work and strong modeling skills, with a PhD preferred. You will help define pre-silicon and silicon memory approaches across accelerator IPs and subsystems.

Qualifications

• 2+ years of silicon architecture, memory design, or related silicon engineering disciplines.
• Understanding of memory technologies and microarchitectures affecting memory-intensive systems.
• Experience building analytical and cycle-accurate models to evaluate memory trade-offs.

Responsibilities

• Analyze memory requirements per workload across accelerator subsystems, including caches, scratchpads and DSP memories.
• Evaluate SRAM options and recommend best fit for each memory.
• Build memory models and power, performance and area comparisons to inform decisions.
• Support studies on memory hierarchy trade-offs, including cache sizing and on-chip vs off-chip memory.
• Track emerging memory technologies and assess their fit for wearable subsystems.
• Correlate memory estimates with pre-silicon and silicon data to improve modeling.
• Work with memory architects, IP, DSP, memory and circuit teams across programs.

Skills

Silicon architecture

Memory design

Memory modeling

PPA analysis

End-to-end memory system

Education

PhD in Electrical Engineering or related field

Tools

SPICE

Memory compiler

Low-voltage SRAM

Cache sizing tools

Job description

Meta Reality Labs is seeking a Memory Architect on the Subsystem Architecture team to drive on-chip memory design for wearable AR/AI enabled chips. You will collaborate with senior memory architects to balance caches, scratchpads, SRAM and memory hierarchy within tight wearable budgets.

The role requires 2+ years in memory-focused silicon work and strong modeling skills, with a PhD preferred. You will help define pre-silicon and silicon memory approaches across accelerator IPs and subsystems.