Senior Physical Design Engineer – High-Performance PHY

Apple, Inc.; Melbourne; In loco; AUD 180.000 - 240.000; Tempo pieno

Descrizione del lavoro

Apple Melbourne is seeking a forward-thinking Physical Design Engineer to drive high-performance PHY and SOC design from RTL to GDSII. You will partner with architecture, CAD, timing and logic teams to deliver robust, power-aware designs that meet tight constraints across a wide range of Apple products.

The role emphasizes floorplanning, clock networks, and implementation of ECOs, with a focus on correct-by-construction methodologies and LVS/DRC accuracy in a cutting-edge hardware environment.

Competenze

• Bachelor’s of Science in Electrical Engineering required.
• Minimum 10 years of relevant industry experience.
• Experience in high PHY/SOC designs.
• Knowledge of floorplanning, power-grid, clocking, and Place & Route.
• Scripting with Perl or Tcl.
• HDL Verilog experience for timing fixes.

Mansioni

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions and power grid.
• Perform block level place and route and meet timing, area and power constraints.
• Generate and Implement ECOs to fix timing, noise and EM IR violations.
• Run Physical Design verification flow and guide LVS/DRC fixes.
• Assist in CAD and physical design methodologies for correct by construction designs.
• Assist in flow development for chip integration.

Conoscenze

Electrical Engineering

Verilog HDL

Perl/Tcl scripting

Physical design

Formazione

Bachelor's in Electrical Engineering

Strumenti

P&R tools

CAD tools

Descrizione del lavoro

Apple Melbourne is seeking a forward-thinking Physical Design Engineer to drive high-performance PHY and SOC design from RTL to GDSII. You will partner with architecture, CAD, timing and logic teams to deliver robust, power-aware designs that meet tight constraints across a wide range of Apple products.

The role emphasizes floorplanning, clock networks, and implementation of ECOs, with a focus on correct-by-construction methodologies and LVS/DRC accuracy in a cutting-edge hardware environment.