Senior Digital Design Engineer - NVLink Fusion RTL Expert

NVIDIA Corporation; Redmond; On-site; AUD 280,000 - 525,000; Full time

Job summary

NVIDIA Corporation is seeking a Digital Design Engineer to join the NVLink Fusion design team in our Semi-Custom Silicon products group. You will analyze requirements, craft micro-architecture, and deliver RTL blocks that meet high performance, area, and power targets.

You will collaborate with architects, verification and SoC integration engineers to select IP solutions and ensure timely delivery. A strong background in high-speed protocols and ASIC flows is essential for success.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 12+ years of relevant work experience.
• Experience with high-speed connectivity protocols (NVLink, PCI-Express, Ethernet, UCIE).
• Proven track record delivering high-bandwidth datapath blocks (data movers, protocol adaptors, network-on-chip, arbiters, schedulers).
• Deep understanding of ASIC design flows and methodologies.
• Strong analytical and interpersonal skills, excellent teammate.

Responsibilities

• Analyze architectural requirements, perform trade-off analysis for implementation, and deliver high-performance, area- and power-efficient RTL blocks.
• Craft micro-architecture specifications, implement in RTL, and deliver fully verified, synthesis- and timing-clean blocks.
• Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers to meet block goals.
• Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.

Skills

NVLink Protocols

PCIe Protocols

Ethernet Protocols

UCIE

High-speed Datapath

Education

Bachelor's or Master's in Electrical or Computer Engineering

Job description

NVIDIA Corporation is seeking a Digital Design Engineer to join the NVLink Fusion design team in our Semi-Custom Silicon products group. You will analyze requirements, craft micro-architecture, and deliver RTL blocks that meet high performance, area, and power targets.

You will collaborate with architects, verification and SoC integration engineers to select IP solutions and ensure timely delivery. A strong background in high-speed protocols and ASIC flows is essential for success.