Senior RTL Design Engineer – Space-Grade ASICs

SpaceX; Redmond; On-site; AUD 236,000 - 387,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical coverage

Dental coverage

Vision coverage

Paid vacation

Paid holidays

Job summary

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink.

You will work with cross‑disciplinary teams—systems, firmware, architecture, design, validation, and ASIC implementation—to deliver high‑reliability chips for space and ground networks. You will define micro-architecture, write RTL in Verilog/SystemVerilog, ensure full verification, and collaborate with the verification team to meet strict timing and synthesis goals.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 5+ years of RTL implementation experience.
• Experience solving clock-domain crossings and power optimization.
• ASIC/SoC integration experience.
• Experience with embedded CPU subsystems and standard bus protocols (AXI/AHB).

Responsibilities

• Evaluate architectural trade-offs based on features, performance requirements and system limitations.
• Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring‑up and validation.

Skills

RTL implementation

Verilog/SystemVerilog

Clock-domain crossing

ASIC/SoC integration

Embedded CPU subsystems

AXI/AHB

High-speed design

Python scripting

HDL simulators

HDL Lint tools

Education

Bachelor’s degree in electrical engineering, computer engineering, or computer science

Tools

HDL simulators

HDL Lint tools

EDA tools

Job description

SpaceX is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink.

You will work with cross‑disciplinary teams—systems, firmware, architecture, design, validation, and ASIC implementation—to deliver high‑reliability chips for space and ground networks. You will define micro-architecture, write RTL in Verilog/SystemVerilog, ensure full verification, and collaborate with the verification team to meet strict timing and synthesis goals.