Senior Engineer Mixed Signal Layout (f/m/div)

Infineon Technologies AG; Villach; On-site; EUR 70,000 - 110,000; Full time

Job summary

Infineon Technologies AG in Austria is seeking an experienced IC layout engineer to drive full-custom layout for ADC mixed-signal components, from schematic through tape-out, with a focus on robustness and manufacturability.

You will lead a small layout team, mentor engineers, and collaborate with ADC design engineers across global teams, applying precise matching, noise isolation, and thorough DRC/LVS/ERC checks to ensure signal and power integrity.

Qualifications

• Bachelor's or master's degree in electrical engineering or equivalent.
• 5+ years hands-on CMOS/FinFET experience.
• Proficiency with Cadence Virtuoso and Calibre.
• Excellent analytical skills to debug layout and verification issues.
• Excellent communication to bridge global teams.
• Ability to lead small layout teams and collaborate with ADC design engineers.
• Fluent in English.

Responsibilities

• Full custom IC layout from schematic to tape-out for ADC mixed-signal components.
• Optimize layout to reduce noise via matching and isolation techniques.
• Perform full-chip physical verification including DRC, LVS, ERC, and antenna checks.
• Analyze and minimize parasitics to preserve signal and power integrity.
• Plan floor planning, pad-ring assembly, and top-level integration with ESD/EM guidelines.
• Provide technical leadership and mentor junior layout engineers.
• Collaborate with ADC Design Engineers across global teams.

Skills

CMOS/FinFET layout

EDA tools proficiency

Analytical debugging

Cross-functional communication

Leadership of small teams

English fluency

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

Siemens Calibre

Job description

Responsibilities

• Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components
• Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends
• Physical Verification: Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks
• Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity
• Top-Level Integration: Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration (EM) guidelines
• Leadership & Mentorship: Provide technical leadership during project execution and mentor junior layout engineers within the team

Qualifications

• A bachelor's or master's degree in electrical engineering or a comparable field
• Ideally 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies
• High proficiency with industry-standard EDA tools (Cadence Virtuoso, Siemens Calibre, etc.)
• Excellent analytical skills to independently debug complex layout and physical verification issues
• Excellent communication skills to bridge technical gaps across global, multidisciplinary engineering teams
• The ability to guide, motivate, and coordinate small layout teams during project execution, and to collaborate closely with ADC Design Engineers
• Fluent in English

We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.