Lead Mixed-Signal IC Layout Engineer (ADC)

Infineon Technologies AG; Villach; On-site; EUR 70,000 - 110,000; Full time

Job summary

Infineon Technologies AG in Austria is seeking an experienced IC layout engineer to drive full-custom layout for ADC mixed-signal components, from schematic through tape-out, with a focus on robustness and manufacturability.

You will lead a small layout team, mentor engineers, and collaborate with ADC design engineers across global teams, applying precise matching, noise isolation, and thorough DRC/LVS/ERC checks to ensure signal and power integrity.

Qualifications

• Bachelor's or master's degree in electrical engineering or equivalent.
• 5+ years hands-on CMOS/FinFET experience.
• Proficiency with Cadence Virtuoso and Calibre.
• Excellent analytical skills to debug layout and verification issues.
• Excellent communication to bridge global teams.
• Ability to lead small layout teams and collaborate with ADC design engineers.
• Fluent in English.

Responsibilities

• Full custom IC layout from schematic to tape-out for ADC mixed-signal components.
• Optimize layout to reduce noise via matching and isolation techniques.
• Perform full-chip physical verification including DRC, LVS, ERC, and antenna checks.
• Analyze and minimize parasitics to preserve signal and power integrity.
• Plan floor planning, pad-ring assembly, and top-level integration with ESD/EM guidelines.
• Provide technical leadership and mentor junior layout engineers.
• Collaborate with ADC Design Engineers across global teams.

Skills

CMOS/FinFET layout

EDA tools proficiency

Analytical debugging

Cross-functional communication

Leadership of small teams

English fluency

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence Virtuoso

Siemens Calibre

Job description

Infineon Technologies AG in Austria is seeking an experienced IC layout engineer to drive full-custom layout for ADC mixed-signal components, from schematic through tape-out, with a focus on robustness and manufacturability.

You will lead a small layout team, mentor engineers, and collaborate with ADC design engineers across global teams, applying precise matching, noise isolation, and thorough DRC/LVS/ERC checks to ensure signal and power integrity.