Senior Staff Digital Verification Engineer-Lead & Innovate

Infineon Technologies; Villach; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

Infineon Technologies in Austria seeks a Senior Staff Engineer Digital Verification to shape verification strategies for digital and mixed-signal designs. You will design verification plans, build advanced environments in SystemVerilog/UVM, and lead a team of verification engineers.

You will write tests for RTL and gate-level, debug complex issues, and collaborate with architects and designers to elevate methodologies. English fluency is required; German language skills are a plus.

Qualifikationen

• University degree in Electrical Engineering, Information Technology, Telematics, or a related field with a focus on electronics.
• At least 6 years of professional experience in digital verification; experience in technical leadership is highly desirable.
• Expert knowledge of SystemVerilog and UVM; solid understanding of SystemVerilog for design.
• Strong scripting skills using bash, tcsh, Python, TCL or similar.

Aufgaben

• Create and define verification plans for digital or digital mixed signal designs.
• Create new and improve existing verification environments in SystemVerilog/UVM.
• Write and execute tests for RTL and gate-level; debug issues in design and verification environments.
• Lead and coordinate other verification engineers in your projects.
• Mentor junior colleagues, consultants and students; cooperate with architects and designers.

Kenntnisse

SystemVerilog & UVM expertise

Scripting: Python/TCL/bash

Leadership experience

English proficiency

German language a plus

Ausbildung

University degree in Electrical Engineering or related field

Tools

SystemVerilog

UVM

Python scripting

Jobbeschreibung

Infineon Technologies in Austria seeks a Senior Staff Engineer Digital Verification to shape verification strategies for digital and mixed-signal designs. You will design verification plans, build advanced environments in SystemVerilog/UVM, and lead a team of verification engineers.

You will write tests for RTL and gate-level, debug complex issues, and collaborate with architects and designers to elevate methodologies. English fluency is required; German language skills are a plus.