Senior Digital & Mixed-Signal Verification Lead

Infineon Technologies AG; Villach; Vor Ort; EUR 90.000 - 120.000; Vollzeit

Zusammenfassung

Infineon Technologies AG is seeking a Senior Staff Engineer in Verification to shape the future of digital verification for mixed-signal designs. You will define verification plans, build advanced environments with SystemVerilog, UVM, and constrained random techniques, and drive tests across RTL and gate-level implementations.

You will lead a team of verification engineers, collaborate with analog and digital designers, and mentor juniors, while pushing continuous improvements in methodologies

Qualifikationen

• University degree in Electrical Engineering, Computer Science, Information Technology or similar.
• 6+ years of Digital Verification experience, leadership helpful.
• Strong SystemVerilog, UVM, and verification tool know-how (Xcelium, Verdi, vManager).
• Good RTL design knowledge and digital or mixed-signal circuits.
• GIT, Python, and other programming languages are a plus.

Aufgaben

• Create and define verification plans for digital verification of mixed-signal designs.
• Develop and improve verification environments using SystemVerilog, UVM, and constrained-random techniques.
• Execute tests on RTL and gate-level; debug design and verification issues.
• Lead and coordinate other verification engineers in projects.
• Collaborate with analog and digital designers and other verification engineers.
• Mentor junior colleagues, consultants and students.
• Drive innovation projects to enhance existing methodologies and flows.

Kenntnisse

SystemVerilog

UVM

Xcelium

Verdi

vManager

RTL design

GIT

Python

Ausbildung

Bachelor's degree in Electrical Engineering/Computer Science or similar

Tools

Xcelium

Verdi

vManager

Jobbeschreibung

Infineon Technologies AG is seeking a Senior Staff Engineer in Verification to shape the future of digital verification for mixed-signal designs. You will define verification plans, build advanced environments with SystemVerilog, UVM, and constrained random techniques, and drive tests across RTL and gate-level implementations.

You will lead a team of verification engineers, collaborate with analog and digital designers, and mentor juniors, while pushing continuous improvements in methodologies