Senior AMS Verification Engineer

IC Resources; Salzburg; Hybrid; EUR 60,000 - 90,000; Full time

Job summary

IC Resources is seeking a Senior Mixed-Signals Verification Engineer in Austria to verify analog and mixed-signal products. The role requires 4+ years of AMS verification and strong SystemVerilog/Verilog-AMS skills, with UVM as a plus.

The position allows remote work within Austria after an initial ramp-up period in the office, with applications restricted to EU residents. Fluency in English is required.

Qualifications

• Industry degree qualified (Masters or Bachelor's).
• 4+ years of experience in AMS verification.
• Strong skills in SystemVerilog and RNM (Verilog-AMS).
• Experience with AMS simulations and debugging.

Responsibilities

• Verify analog/mixed-signal (AMS) products.
• Develop Real-Number models (SystemVerilog, WREAL, Verilog-AMS) for AMS IPs/blocks.
• Create analog/mixed-mode testbenches and verify blocks/subsystems.
• Contribute to verification concepts and specifications for mixed-signal projects.
• Align and track testbenches and stimuli to the verification plan.

Skills

AMS Verification

SystemVerilog

Verilog-AMS/RNM

Testbenches

UVM

Education

Masters or Bachelor's Degree

Tools

RNM (Verilog-AMS)

SystemVerilog

Job description

Are you passionate about cutting-edge technologies and future-oriented projects in semiconductor design? Join a market leader in turnkey solutions, offering the opportunity to work on a diverse range of products across Automotive, Compute, Industrial, Medical, and other markets. This position can be remote within Austria after a ramp up time in the office. Remote from another country is not possible and only applications with an existing workpermti can be considered!

As a Senior Mixed-Signals Verification Engineer, you will:

• Perform verification of Analog and Mixed-Signal (AMS) products.
• Develop Real-Number models (SystemVerilog, WREAL, Verilog-AMS) for analog and mixed-signal IPs/blocks, ensuring consistency with schematics.
• Create analog/mixed-mode testbenches and verify blocks and subsystems.
• Contribute to verification concepts and specifications for mixed-signal projects.
• Align and track the implementation of testbenches and stimuli according to the verification plan.

Qualifications:

• Industry degree qualified with a Masters or Bachelors Degree
• 4+ years of experience in AMS Verification
• Strong skills in SystemVerilog and RNM (Verilog AMS)
• Experience with AMS simulations and debugging.
• UVM experience is a plus
• Proficiency in English

Only application from within the EU will be considered.