Wearables IP Verification Engineer - Power & Performance

Spectraforce Technologies; Sunnyvale (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Spectraforce Technologies seeks a Design Verification Engineer III for a 6-month onsite role in Sunnyvale, CA. Responsibilities include developing DV plans, building SystemVerilog/UVM testbenches, and driving coverage closure across IPs and subsystems.

The candidate will perform power/performance measurements using PPA RTL tools, triage RTL regressions, and contribute to automation via Python. BS in EE/CS required; MS preferred.

Qualifications

• Proven SystemVerilog + UVM verification experience.
• Functional coverage, constrained-random testing and SVA.
• Strong RTL debug with VCS/Xcelium/Questa and Verdi.
• Python scripting for automation.

Responsibilities

• Develop and execute verification plans for RTL blocks/IPs.
• Build and maintain SystemVerilog/UVM testbenches and tests.
• Drive functional coverage and assertion closure; triage regressions.
• Perform power/performance measurement across design stages with PPA RTL tools; correlate results with post-silicon data.
• Develop automation for verification/regression and power measurement workflows (Python).

Skills

SystemVerilog/UVM testbench

Functional coverage / SVA

RTL debugging + Python automation

Education

BS in Electrical/Computer Engineering or CS

Tools

PrimeTime PX

UPF / power-aware verification

Palladium / Zebu emulation

Job description

Spectraforce Technologies seeks a Design Verification Engineer III for a 6-month onsite role in Sunnyvale, CA. Responsibilities include developing DV plans, building SystemVerilog/UVM testbenches, and driving coverage closure across IPs and subsystems.

The candidate will perform power/performance measurements using PPA RTL tools, triage RTL regressions, and contribute to automation via Python. BS in EE/CS required; MS preferred.