Design Verification Engineer III

Spectraforce Technologies; Sunnyvale (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Spectraforce Technologies seeks a Design Verification Engineer III for a 6-month onsite role in Sunnyvale, CA. Responsibilities include developing DV plans, building SystemVerilog/UVM testbenches, and driving coverage closure across IPs and subsystems.

The candidate will perform power/performance measurements using PPA RTL tools, triage RTL regressions, and contribute to automation via Python. BS in EE/CS required; MS preferred.

Qualifications

• Proven SystemVerilog + UVM verification experience.
• Functional coverage, constrained-random testing and SVA.
• Strong RTL debug with VCS/Xcelium/Questa and Verdi.
• Python scripting for automation.

Responsibilities

• Develop and execute verification plans for RTL blocks/IPs.
• Build and maintain SystemVerilog/UVM testbenches and tests.
• Drive functional coverage and assertion closure; triage regressions.
• Perform power/performance measurement across design stages with PPA RTL tools; correlate results with post-silicon data.
• Develop automation for verification/regression and power measurement workflows (Python).

Skills

SystemVerilog/UVM testbench

Functional coverage / SVA

RTL debugging + Python automation

Education

BS in Electrical/Computer Engineering or CS

Tools

PrimeTime PX

UPF / power-aware verification

Palladium / Zebu emulation

Job description

Job Title: Design Verification Engineer III

Duration: 06 Months (Possible extension)

Location: Onsite 3 days in Sunnyvale, CA

Job Description

• Design Verification engineer for wearables silicon accelerator IPs - testbench development, coverage-driven verification, RTL debug, and power/performance measurement.

Top 3 Must-Have Skills

• SystemVerilog / UVM testbench development.
• Functional coverage + assertion-based verification and coverage closure.
• RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.

Good to have skills

• Experience with power measurement tools - PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
• Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
• Formal verification and/or emulation (Palladium / Zebu) experience.
• Familiarity with the RTL-to-GDSII flow.
• Data analysis / ML approaches for coverage or debug triage.
• Previous Meta experience preferred.

Education

• BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).

Responsibilities

• Develop and execute verification plans for RTL blocks/IPs across the subsystem.
• Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
• Drive functional coverage and assertion (SVA) closure; run and triage regressions.
• Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
• Build power/perf dashboard for tracking and publishing
• Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
• Contribute to automation of verification/regression and power/performance measurement flows (Python).

Minimum Qualifications

• Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
• Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
• Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
• Working knowledge of RTL design principles and digital design fundamentals.
• Proficiency in Python (or Perl) scripting for automation.

Story Behind the Need - Business Group & Key Projects:

• We are seeking a Power Measurement Design Verification Engineer to develop and execute DV test strategies focused on power and performance characterization at the IP and SoC level. This role is critical to enabling accurate pre-silicon power estimation, driving power optimization decisions, and maintaining automated power reporting infrastructure