Design Engineer III

Tech Mahindra; Sunnyvale, Northern (CA, KY); On-site; USD 131,000 - 160,000; Full time

Benefits offered by this job

Medical

Vision

Dental

Life insurance

Disability insurance

Paid time off

Job summary

Tech Mahindra in Sunnyvale, CA is seeking a Design Verification Engineer for wearables silicon accelerator IPs; you will develop testbenches, drive coverage-driven verification, and debug RTL with VCS/Xcelium/Questa.

Responsibilities include building verification plans, writing constrained-random tests, and driving coverage closure; power/performance measurement across design stages will be performed using PPA tools, with collaboration across teams and daily coordination with teammates.

Qualifications

• Minimum qualifications include SystemVerilog + UVM verification with testbench experience.
• Functional coverage, constrained-random, and SVA assertions.
• RTL debugging with VCS/Xcelium/Questa and waveform analysis.
• Proficiency in Python scripting for automation.

Responsibilities

• Develop and execute verification plans for RTL blocks/IPs across the subsystem.
• Build and maintain SystemVerilog/UVM testbenches; write directed and constrained tests.
• Drive functional coverage and assertion (SVA) closure; run and triage regressions.
• Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
• Build power/perf dashboard for tracking and publishing Debug RTL failures and provide actionable feedback to the design and verification teams.
• Contribute to automation of verification/regression and power/performance measurement flows (Python).

Skills

SystemVerilog + UVM

RTL blocks

VCS

Xcelium

Questa

Python scripting

Education

BS in Electrical/CS

MS preferred

Tools

VCS

Xcelium

Questa

Verdi

Job description

A Bachelor’s or Higher Degree is the minimum entry required for the position

Image

Job Description

• Skill Set : SystemVerilog + UVM verification,RTL blocks,VCS / Xcelium / Questa

About the role: Design Verification engineer for wearables silicon accelerator IPs — testbench development, coverage-driven verification, RTL debug, and power/performance measurement.

Responsibilities
Develop and execute verification plans for RTL blocks/IPs across the subsystem.
Build and maintain SystemVerilog/UVM testbenches; write directed and constrained-random tests.
Drive functional coverage and assertion (SVA) closure; run and triage regressions.
Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
Build power/perf dashboard for tracking and publishing Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
Contribute to automation of verification/regression and power/performance measurement flows (Python).

Minimum Qualifications
Proven SystemVerilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
Working knowledge of RTL design principles and digital design fundamentals.
Proficiency in Python (or Perl) scripting for automation.

Preferred Qualifications
Experience with power measurement tools — PrimeTime PX (PTPX) or equivalent (e.g., PrimePower).
Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
Formal verification and/or emulation (Palladium / Zebu) experience.
Familiarity with the RTL-to-GDSII flow.
Data analysis / ML approaches for coverage or debug triage.
Previous Meta experience preferred.

Education: BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).
Top 3 Must-Have Skills
SystemVerilog / UVM testbench development.
Functional coverage + assertion-based verification and coverage closure.
RTL debug (VCS/Xcelium) + Python automation; power/perf measurement.

Responsibilities
Day-to-day: build/run testbenches and regressions, analyze coverage, debug failures, and measure power/performance with the design team; work daily with 2-3 teammates and other CWs.
Emphasis on front-end DV (RTL verification), aligned with prior HM guidance on #68919.

The pay range for this role is $145k per annum including any bonuses or variable pay. Tech Mahindra also offers benefits like medical, vision, dental, life, disability insurance and paid time off (including holidays, parental leave, and sick leave, as required by law).

Tech Mahindra is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin, or disability. All applicants will be evaluated solely on the basis of their ability, competence, and performance of the essential functions of their positions with or without reasonable accommodations. Reasonable accommodations also are available in the hiring process for applicants with disabilities. Candidates can request a reasonable accommodation by contacting the company ADA Coordinator [e-mail].