Wafer-Level Yield Analysis Engineer

Intel; Hillsboro (OR); On-site; USD 99,000 - 140,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel in Hillsboro, Oregon seeks an Experienced LYA Engineer to support back-end package assembly and wafer-level testing. The role focuses on design, test, checkout, and characterization of assembly technologies in a lab-based, on-site environment.

You will set priorities, drive results across boundaries, and work with internal teams and external partners to identify root causes of in-line failures and improve yield with innovative techniques.

Qualifications

• Bachelor's or Master's in Materials Science and Engineering, Mechanical Engineering, Chemical Engineering, Electrical Engineering, or Chemistry/Physics or related field.
• Experience in a lab environment is preferred.
• Experience with destructive and optical analysis techniques (SEM, x-ray, microscopy, CSAM, ion milling, TEM, FIB).
• Experience with electrical fault isolation and failure analysis using hand probe, curve trace, auto probing, TDR, EOTPR, EBAC, RIDR, ELITE.
• Knowledge of packaging or die mapping software (Mentor Graphics, SysNav/CadNav, FIELD) and SQL/JMP is a plus.

Responsibilities

• Work across team boundaries to achieve program objectives and deliverables.
• Interface with internal teams and external suppliers to improve yield and drive innovation.
• Conduct hands-on lab work and define data acquisition and analysis plans.
• Develop failure analysis techniques and packaging improvements in manufacturing.
• Communicate findings through reports to yield engineers and customers.

Skills

Analytical skills

Problem-solving

Communication skills

Team collaboration

Adaptability

Lab experience

Education

Bachelor's Degree

Master's Degree

Tools

SEM

X-ray

TEM

FIB

Mentor Graphics

SysNav/CadNav

SQL scripting

JMP

Job description

Intel in Hillsboro, Oregon seeks an Experienced LYA Engineer to support back-end package assembly and wafer-level testing. The role focuses on design, test, checkout, and characterization of assembly technologies in a lab-based, on-site environment.

You will set priorities, drive results across boundaries, and work with internal teams and external partners to identify root causes of in-line failures and improve yield with innovative techniques.