Design Verification Engineer

Wipro; Santa Clara (UT); On-site; USD 60,000 - 140,000; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off

Job summary

Wipro is seeking a verification engineer with 3–5 years of HVL experience to design UVM/SystemVerilog environments for IP, subsystem and SoC testing. You will develop directed and random test cases, analyze coverage, and work with RTL teams to debug issues while executing regressions and driving improvements.

Ideal candidates understand SV/UVM, AMBA protocols, and power-aware simulations; you will collaborate with DFT/PD/RTL groups and document environments, plans and results for reviews.

Qualifications

• 3–5 years of HVL verification experience.
• Strong understanding of SV and UVM.
• Experience with AMBA protocols.

Responsibilities

• Build UVM/SystemVerilog verification environments for IP/subsystem/SoC testing.
• Develop directed and random testcases and perform coverage analysis.
• Debug simulation failures with RTL designers to resolve issues.
• Execute regression runs and contribute to continuous improvements.
• Integrate and run power-aware simulations using UPF/CPF as needed.
• Collaborate with DFT/PD/RTL teams and post-silicon validation.
• Document test environments, test plans and results.

Skills

SV/UVM

Debugging

AMBA protocols

Test plans

UVM SystemVerilog

Testbench development

Coverage analysis

Regression tests

Power-aware sim

DFT/RTL collaboration

Documentation

Tools

UPF/CPF

Verilog/SystemVerilog

VCS/Verdi

Job description

Job Description

Job Description

Key Responsibilities

• Strong understanding of SV and UVM and good debugging skills.
• Understanding of AMBA protocols.
• Understand design specs and develop test plans based on functional and architectural requirements
• Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
• Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
• Debug simulation failures and work closely with RTL designers to resolve issues
• Execute regression runs, analyze results, and contribute to continuous improvements
• Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
• Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
• Document test environments, testplans, and results for internal and external reviews
• Mandatory Skills: VLSI HVL Verification
• Experience: 3-5 Years

The expected compensation for this role ranges from $60,000 to $140,000 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

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