Principle VLSI/ ASIC Design Engineer

HP Enterprise; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Subsidized health insurance

Industry-leading maternity/paternity‑t

Hybrid work model

Annual equity awards

Job summary

HP Enterprise is seeking an experienced Principle VLSI/ASIC Design Engineer in Sunnyvale, CA, to lead architecture, RTL design, and analysis of complex SoC solutions. The role shapes technology roadmaps, collaborates across teams, and ensures production-ready designs.

The candidate will mentor engineers, influence product strategy, and drive design methodologies while delivering high-performance, scalable ASIC blocks for networking and compute applications.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.

Responsibilities

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectural approaches, microarchitectures, design methodologies, and implementation plans.
• Design, develop, and modify complex RTL blocks using industry-standard HDLs.
• Drive RTL implementation from architecture through synthesis and timing closure.
• Analyze tradeoffs on performance, power, area, and MTTR.

Skills

RTL design

ASIC/VLSI architecture

Networking ASICs

High-speed interfaces

Design exploration

Mentoring engineers

Analytical modeling

SystemVerilog

Verilog

Timing analysis

Education

Electrical/Computer Engineering or CS degree

Tools

Synthesis tools

Formal verification tools

Automation & tooling

Job description

• The Principle VLSI/ASIC Design Engineer is responsible for the architecture, RTL design, implementation, and analysis of complex VLSI components and system-on-chip (SoC) solutions
• This role contributes to early-stage architecture and design exploration and carries concepts through detailed design implementation for networking, compute, and other complex SoC applications
• The engineer will serve as a recognized technical authority in ASIC and VLSI design, influencing product strategy, technology roadmaps, architectural direction, and implementation methodologies across organizations and business units
• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications
• Define architectural approaches, microarchitectures, design methodologies, and implementation plans aligned with product requirements and technology roadmaps
• Design, develop, and modify complex RTL blocks using industry-standard hardware description languages and design practices
• Drive RTL implementation from architectural definition through synthesis, physical implementation support, timing closure, and production readiness
• Analyze design tradeoffs involving performance, power, area, scalability, reliability, and time to market
• Develop and evaluate VLSI components and hardware systems across multiple platforms and product organizations
• Conduct design reviews and evaluate product designs for compliance with architecture, implementation guidelines, quality standards, and industry best practices
• Establish operating data and performance expectations through analytical modeling, simulation, prototyping, and experimental evaluation
• Provide tangible, data-driven feedback to improve product quality, reduce design risk, and mitigate potential product failures
• Contribute to organization-wide ASIC design architectures, methodologies, and standards
• Create integration plans for incorporating new technologies, IP, design practices, and implementation improvements into existing architectures
• Identify emerging technologies, innovations, tools, and external partnerships that support business objectives and technology roadmaps
• Review material specifications, hardware designs, electrical component requirements, and related technical documentation
• Collaborate with architecture, hardware, firmware, verification, physical design, systems, software, manufacturing, and external development teams
• Influence technical decisions made by business leadership, development partners, suppliers, and industry standards organizations
• Provide technical leadership for significant projects and programs, connecting teams across functions around common objectives
• Mentor less-experienced engineers and promote design innovation, engineering excellence, and knowledge sharing
• Serve as an internal authority on ASIC and VLSI engineering, providing consultation across organizations and business units

Benefits

• Subsidized health insurance, retirement programs and paid time off, including an industry-leading maternity and paternity leave package
• Recognition for your contributions, and potential participation in long-term incentives like annual equity awards
• The chance to earn an annual bonus based on performance
• A hybrid, flexible work model that ensures connectivity, a commitment to our culture and continued impact for team members
• Opportunities for personal and professional development to help you reach your career goals

The role requires strong technical leadership, innovation, cross-functional collaboration, and the ability to mentor engineers while delivering high-quality, scalable, and production-ready designsDemonstrated experience designing complex RTL blocks for networking, compute, communications, storage, or other advanced SoC applicationsExperience leading architecture and design exploration through RTL implementation and product integrationDesign verification experience is not required but is highly desirableTypically, 9 + or more years of experience in ASIC, VLSI, SoC, or related hardware designBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; equivalent experience may be consideredProven ability to influence decisions across business units, functions, senior leadership, external partners, and industry organizationsIs recognized as an internal authority in key ASIC, RTL, and VLSI technology areasUnderstanding of ASIC development flows, including architecture, microarchitecture, RTL coding, synthesis, timing analysis, physical design interaction, and design signoffStrong collaboration skills and experience working effectively across geographically distributed, cross-functional teamsProvides technical leadership for major projects and programs and unites teams around common goalsAbility to mentor engineers and provide technical direction without direct management responsibilityAbility to evaluate design alternatives and make recommendations based on performance, power, area, cost, risk, and scheduleStrong written and verbal communication skills, with the ability to explain complex technical concepts to both technical and executive audiencesDemonstrated innovation, including the development or adoption of new technologies, methodologies, or design practicesStrong analytical, problem-solving, and technical decision-making skillsAbility to communicate architectural proposals, design plans, tradeoffs, risks, and results effectivelyActively mentors engineers and contributes to the broader technical communityDelivers unique, long-lasting improvements in areas such as time to market, product quality, cost reduction, scalability, and customer valueMakes substantial technical contributions to significant HPE products, programs, or strategic architectural initiativesExperience with design modeling, simulation, performance analysis, and empirical evaluation methodologiesProven experience developing complex RTL using Verilog, System Verilog, or comparable hardware description languagesAdvanced knowledge of ASIC and VLSI design principles, digital logic, RTL design, and SoC developmentExperience defining and improving design methodologies, tools, automation, and engineering practicesActs as a go-to creator and innovator for critical business and technology challengesExperience with networking ASICs, data-processing units, switching, routing, acceleration, storage, or high-performance computing architecturesExperience with high-speed interfaces, packet-processing pipelines, memory subsystems, interconnects, or performance-critical datapathsFamiliarity with formal verification, constrained-random verification, coverage methodologies, or verification planningExperience with low-power design, clock-domain crossing, reset-domain crossing, DFT, and design-for-reuse methodologiesKnowledge of industry standards and leading-edge ASIC implementation technologiesExperience working with outsourced development partners, IP vendors, foundries, or semiconductor suppliers