Verification Engineer — Photonics ASIC/SoC

Lumilens; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Lumilens is seeking an experienced ASIC/SoC verification engineer to verify blocks of a first‑of‑its‑kind chiplet. You will build and extend UVM testbenches, write directed and constrained‑random tests, and drive functional coverage to closure, guiding verification across simulation and emulation.

The role offers hands‑on opportunities to grow with a fast‑moving startup. Ideal candidates have 3+ years in ASIC/SoC verification, strong UVM/SystemVerilog skills, and experience with regression/CI

Qualifications

• BS or MS in Electrical/Computer Engineering.
• 3+ years of ASIC/SoC functional verification.
• Strong UVM/SystemVerilog; constrained‑random and coverage‑driven verification.
• Testbench development and coverage closure.
• Strong debug skills across simulation; scripting in Python, Perl, or TCL.
• Familiarity with regression/CI flows and failure triage.

Responsibilities

• Build and extend UVM testbenches for assigned blocks and subsystems.
• Write directed and constrained-random tests; develop functional coverage and drive it to closure.
• Verify in‑house engines against an algorithmic golden model.
• Integrate and use VIP (e.g., UCIe) and run compliance, link‑training, loopback, and lane‑repair scenarios.
• Run regressions, triage failures, and help maintain the CI/regression flow.
• Register (UVM RAL) verification, firmware co‑simulation, and boot flows on the MCU subsystem.
• Mixed‑signal co‑simulation — verifying digital blocks against analog/mixed‑signal models.
• Support hardware‑assisted verification — emulation and FPGA prototyping.
• Participate in gate‑level and low‑power (UPF) verification during signoff.
• Collaborate with design, architecture, modelling, and DFT teams.

Skills

UVM

SystemVerilog

Testbench development

Coverage analysis

Python scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

VIP tools

Palladium/Veloce

Job description

Lumilens is seeking an experienced ASIC/SoC verification engineer to verify blocks of a first‑of‑its‑kind chiplet. You will build and extend UVM testbenches, write directed and constrained‑random tests, and drive functional coverage to closure, guiding verification across simulation and emulation.

The role offers hands‑on opportunities to grow with a fast‑moving startup. Ideal candidates have 3+ years in ASIC/SoC verification, strong UVM/SystemVerilog skills, and experience with regression/CI