Verification Lead (Lead DV)

Lumilens; San Jose (CA); Sur place; USD 150 000 - 200 000; Plein temps

Avantages offerts par ce poste

Competitive salary

Comprehensive benefits package

Professional development opportunities

Résumé du poste

Lumilens in San Jose is seeking an experienced ASIC/SoC verification expert to lead their DV team. You will own the full DV strategy for a groundbreaking chiplet, defining methods before the RTL is ready. The role requires over 10 years of experience in verifying complex SoCs and leading a team.

You will also manage a collaborative environment and ensure rigorous verification processes. Competitive salary and comprehensive benefits are offered, including health and professional development.

Qualifications

• 10+ years ASIC/SoC verification experience.
• Proven leadership verifying complex digital SoCs.
• Deep knowledge in UVM/SystemVerilog and coverage-driven verification.

Responsabilités

• Own the full DV strategy and verification plan.
• Stand up regression/CI infrastructure before RTL delivery.
• Lead and grow the DV team across multiple domains.

Connaissances

ASIC/SoC verification

Team leadership

UVM/SystemVerilog

Hardware-assisted verification

Mixed-signal verification

Regression/CI

Description du poste

About Lumilens

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.

We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.

This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.

If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.

About the Role

You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.

What You'll Own

• The full DV strategy: verification plan, coverage model (functional + code), UVM architecture, and signoff criteria from block to full-chip.

• Stand up regression/CI infrastructure and nightly runs before design hands over first RTL.

• Verification of the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.

• Hardware-assisted verification: bring up and own the emulation / FPGA-prototyping methodology.

• UCIe VIP and compliance, link-training, loopback, lane-repair scenarios, bit-exact transparency and more.

• Performance and throughput verification.

• UVM register verification, firmware co-simulation, and boot flows on the MCU subsystem.

• Mixed-signal co-simulation — verifying the digital front end against behavioral models of analog/mixed-signal blocks.

• Gate-level and low-power (UPF) verification as part of signoff.

• Lead and grow the DV team (across FEC, UCIe, MCU, datapath, and full-chip).

Required

• 10+ years ASIC/SoC verification, with team leadership on at least one complex SoC from plan to tapeout.
• Proven leadership verifying large, complex digital SoCs / subsystems, including interconnect fabric and full-chip closure.
• Deep UVM/SystemVerilog; coverage-driven verification; constrained-random methodology.
• Hands-on with hardware-assisted verification — emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
• Comfortable with mixed-signal verification (Verilog-AMS or SV real models).
• Regression/CI at scale (grid, triage automation), and rigorous coverage closure.

Preferred

• High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification experience.
• UCIe, PCIe/CXL, Ethernet, UALink or comparable die-to-die / link-layer VIP and compliance experience.
• NIC Cards, Ethernet/IB Switches, Cache-coherency verification (multi-core / coherent fabric).
• Low-power/UPF and gate-level simulation methodology.
• Performance-verification methodology.
• Formal verification for control/interlock logic; portable-stimulus.

What We Offer

• Competitive salary commensurate with experience
• Comprehensive benefits package including health, dental, and vision
• Professional development opportunities and certification support
• Access to cutting-edge technology and cloud platforms
• Collaborative work environment with cross-functional teams

Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.