Top Secret FPGA Engineer II – Onsite, Plano

Socket.dev; Plano (TX); On-site; USD 69,000 - 131,000; Full time

Job summary

RTX in Plano, TX is seeking an FPGA Engineer II to develop FPGA designs for AMD (Xilinx), Altera, and Microchip devices. You will code in VHDL/Verilog, verify with constrained tests, and collaborate with systems engineers from requirements to production release.

The role requires a DoD Top Secret clearance and U.S. citizenship. Onsite work in Plano, TX and a strong background in FPGA/ASIC design with lab experience are essential.

Qualifications

• Typically requires a STEM degree with a minimum of 2 years of relevant experience.
• Experience with FPGA/ASIC design or verification (VHDL/Verilog or SystemVerilog).
• Hands-on lab integration and debugging of FPGA/ASIC devices.
• Experience with AMD (Xilinx), Altera and/or Microchip devices and tools (Vivado/Quartus/Libero).
• Git, code reviews, and team-based release processes.

Responsibilities

• Provide full lifecycle support of production-quality FPGA designs for major vendors/devices.
• Generate FPGA designs for multi-gigabit interfaces, RF DSP, controls, and embedded processing.
• Assist with architecture development of FPGA-based systems and CONOPS.
• Code in VHDL for reliability and maintainability.
• Support design verification with directed and constrained tests and track coverage.
• Report execution status within budget/schedule using an agile framework.
• Create documentation including requirements, verification plan, and user guides.
• Engage as an individual contributor and present work to leadership.

Skills

FPGA design

VHDL/Verilog

SystemVerilog

Git

Python/C

CI/CD

Questa/RivieraPro

Education

STEM degree

Tools

Vivado

Quartus Pro

Libero

Questa

RivieraPro

Git

Job description

RTX in Plano, TX is seeking an FPGA Engineer II to develop FPGA designs for AMD (Xilinx), Altera, and Microchip devices. You will code in VHDL/Verilog, verify with constrained tests, and collaborate with systems engineers from requirements to production release.

The role requires a DoD Top Secret clearance and U.S. citizenship. Onsite work in Plano, TX and a strong background in FPGA/ASIC design with lab experience are essential.