Senior FPGA/ASIC Design Engineer — DoD-Clearance Ready

RTX; McKinney (TX); On-site; USD 87,000 - 165,000; Full time

Benefits offered by this job

Medical coverage

Dental coverage

Vision coverage

Life insurance

Short-term disability

Long-term disability

401(k) match

Flexible spending accounts

Flexible work schedules

Employee assistance program

Employee Scholar Program

Parental leave

Paid time off

Holidays

Job summary

RTX is seeking an experienced FPGA/ASIC design engineer based in McKinney, TX to define system‑level requirements and develop digital architectures. You will implement RTL designs, verify modules, and support timing, power, and functional analyses in a collaborative lab setting. The role requires 5+ years of FPGA/ASIC experience, proficiency with Xilinx/Altera devices, and strong scripting skills.

A DoD Secret clearance and U.S. citizenship are required.

Qualifications

• Requires BS in STEM and 5+ years FPGA/ASIC design, RTL development, and verification.
• Experience with Xilinx/Altera FPGAs or related devices is required.
• Experience with high‑speed interfaces (PCIe, GbE, VPX) and debugging/scripting (Python/Perl/Shell) is essential.
• Ability to obtain and maintain a U.S. government security clearance is required.

Responsibilities

• Define ASIC/FPGA requirements from system specs and develop digital architectures.
• Implement RTL designs and perform timing, power, and functional analyses.
• Integrate and verify FPGA modules in a lab using standard simulation and hardware tools; collaborate with cross‑functional teams.

Skills

FPGA design

ASIC design

RTL development

Verification

Xilinx/Altera FPGAs

High-speed interfaces

Python/Perl/Shell

Education

Bachelor of Science in STEM

Tools

SystemVerilog

Verilog

VHDL

Python scripting

MATLAB

Job description

RTX is seeking an experienced FPGA/ASIC design engineer based in McKinney, TX to define system‑level requirements and develop digital architectures. You will implement RTL designs, verify modules, and support timing, power, and functional analyses in a collaborative lab setting. The role requires 5+ years of FPGA/ASIC experience, proficiency with Xilinx/Altera devices, and strong scripting skills.

A DoD Secret clearance and U.S. citizenship are required.