Top-Level PD Architect: Chip Floorplan & Power

ACL Digital; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ACL Digital is seeking a Senior Principal Physical Design Engineer to take ownership of the top-level floorplan and global power networks for its next-generation architecture.

The ideal candidate will have proven expertise in full-chip integration, mastery of Cadence Innovus and Synopsys Fusion Compiler, and the ability to manage timing budgets and EM/IR sign-off workflows. Exceptional collaboration skills are essential to work closely with both internal and external teams.

Qualifications

• Proven track record of owning full-chip top-level integration and floorplanning.
• Expertise in Cadence Innovus and Synopsys Fusion Compiler.
• Strong background in timing budgets and EM/IR sign-off workflows.

Responsibilities

• Own the top-level floorplan for next-generation architecture.
• Manage global power networks and timing budgets.
• Bridge technical gaps between internal and external teams.

Skills

Full-chip top-level integration

Expert-level mastery of Cadence Innovus

Expert-level mastery of Synopsys Fusion Compiler

Top-level SDC authoring

Timing budgets and EM/IR sign-off

Collaboration with ASIC/IP vendors

Job description

ACL Digital is seeking a Senior Principal Physical Design Engineer to take ownership of the top-level floorplan and global power networks for its next-generation architecture.

The ideal candidate will have proven expertise in full-chip integration, mastery of Cadence Innovus and Synopsys Fusion Compiler, and the ability to manage timing budgets and EM/IR sign-off workflows. Exceptional collaboration skills are essential to work closely with both internal and external teams.