Senior Physical Design Engineer – Low-Power MCU/SoC

Microchip Technology Inc.; Chandler (AZ); Híbrido; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Microchip Technology Inc. in Chandler, AZ seeks a Senior Engineer II in Physical Design to drive complex mixed-signal, low-power PD implementations and deliver tapeout-ready silicon.

You will lead floorplanning, placement, routing, clock tree synthesis, and signoff, partnering with IP, synthesis, and CAD teams. Candidates need 5+ years in Physical Design, strong TCL/PERL/Shell scripting, and proficiency with Innovus, Fusion Compiler, Calibre, Verilog and VHDL.

Formación

• Bachelor or Master in Electrical/Electronic Engineering required.
• 5+ years hands-on Physical Design experience.
• Strong place-and-route and low-power design knowledge.
• Proficient in TCL, PERL, and Shell scripting.
• Experience with Verilog or VHDL.

Responsabilidades

• Implement complex mixed-signal, low-power designs and deliver GDSII flow.
• Perform floorplanning, placement, routing, and clock tree synthesis.
• Lead timing, signal integrity, and power integrity analyses and signoff.
• Develop and refine physical design flows and methodologies.
• Collaborate with IP teams, CAD vendors, and cross-functional groups.

Conocimientos

Place & route

Low power design

EDA tools: Innovus

EDA tools: Fusion Compiler

EDA tools: Calibre

Verilog

VHDL

TCL scripting

PERL scripting

Shell scripting

Clock tree synthesis

Debugging

Educación

Bachelor of Engineering in Electrical / Electronic Engineering

Master of Engineering in Electrical / Electronic Engineering

Herramientas

Verilog

VHDL

Innovus

Fusion Compiler

Calibre

Redhawk

Starrcxt

Descripción del empleo

Microchip Technology Inc. in Chandler, AZ seeks a Senior Engineer II in Physical Design to drive complex mixed-signal, low-power PD implementations and deliver tapeout-ready silicon.

You will lead floorplanning, placement, routing, clock tree synthesis, and signoff, partnering with IP, synthesis, and CAD teams. Candidates need 5+ years in Physical Design, strong TCL/PERL/Shell scripting, and proficiency with Innovus, Fusion Compiler, Calibre, Verilog and VHDL.