Thermal Modeling Lead for CPU Cores & SoC

AMD; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a Lead Physical Design Engineer in Santa Clara, CA to ensure CPU Cores and SOC meet thermal and silicon performance targets. The role focuses on physical design methodology and power/thermal constraints across IPs, driving cross-functional alignment and on-time delivery.

You will lead with a strong background in physical design, EDA tools, and high‑performance SoC/IP design, collaborating with architecture, package modeling, and verification teams to meet milestones and enable

Qualifications

• Bachelor's or Master's degree in computer engineering or electrical engineering.
• Extensive EDA tool experience with physical design.
• Strong knowledge of physical design power and performance metrics.
• Experience with high-performance SoC/IP design.
• Familiarity with package models and advanced packaging designs.
• Experience collaborating with pre-silicon design and package modeling teams.
• Scripting and flow automation experience.

Responsibilities

• Drive development and alignment of thermal modeling methodology, collaborating with Package modeling teams across AMD products.
• Drive new design and analysis methodologies to improve product thermal profile.
• Translate product usage model, workload, and package requirements into IP performance, power, and thermal constraints and align with product performance-power models.
• Drive thermal product requirements cross-function, managing critical deliverables at key project milestones.

Skills

Physical Design

EDA tools

Power & Thermal

SoC/IP design

Scripting

Cross-functional leadership

Education

Bachelor's or Master's in Computer Engineering or Electrical Engineering

Tools

EDA tools

Job description

AMD is seeking a Lead Physical Design Engineer in Santa Clara, CA to ensure CPU Cores and SOC meet thermal and silicon performance targets. The role focuses on physical design methodology and power/thermal constraints across IPs, driving cross-functional alignment and on-time delivery.

You will lead with a strong background in physical design, EDA tools, and high‑performance SoC/IP design, collaborating with architecture, package modeling, and verification teams to meet milestones and enable