Architecting Next-Gen CPU Power & Performance

Advanced Micro Devices; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Advanced Micro Devices (AMD) is seeking a leadPPA Architect in Santa Clara, CA, to ensure CPU Core & Cache complexes meet performance and reliability targets. You will interface with CPU IP, Embedded BU usage models, and power/thermal teams to drive architecture decisions and program readiness.

The role requires strong leadership across architecture, physical design, FW/BIOS, SIPI, and platform partners, with a track record of delivering complex cross-functional initiatives on time.

Qualifications

• BS/MS in EE/CE with 7-10 years of relevant experience.
• Proven ability to lead cross-functional execution on SoC projects.
• Knowledge of PDN and PI principles and reliability requirements.

Responsibilities

• Align Product Requirements with Cores IP.
• Drive alignment on power delivery architecture and platform definition.
• Lead thermal modeling and margin requirements.
• Translate usage model and reliability into IP constraints.
• Coordinate cross-functional reviews across SoC architecture and package.
• Own a closure mechanism for open items on performance topics.

Skills

SoC architecture

Power delivery

Thermal management

Cross-functional leadership

FW/BIOS validation

Packaging/platform

Program milestone readiness

Education

BS/MS in EE/CE (or equivalent)

Tools

SIPI

Job description

Advanced Micro Devices (AMD) is seeking a leadPPA Architect in Santa Clara, CA, to ensure CPU Core & Cache complexes meet performance and reliability targets. You will interface with CPU IP, Embedded BU usage models, and power/thermal teams to drive architecture decisions and program readiness.

The role requires strong leadership across architecture, physical design, FW/BIOS, SIPI, and platform partners, with a track record of delivering complex cross-functional initiatives on time.